Abstract: An object is to provide a digital quadrature detection circuit wherein, without making the circuit complicated and without lowering performance, the operating frequency can be lowered and power consumption can be reduced. There are provided: a quasi-synchronous detector that takes the exclusive logical sum of a binary-converted intermediate frequency signal and a carrier signal, sampling means that respectively sample the output of the quasi-synchronous detector at M phases (where M is an integer of 1 or more) for each symbol, a bit adder that generates an M-bit parallel signal from the output signals of these, and low-pass filters that extract the low frequency components from this output. Whereas conventionally a 100-times clock pulse was employed in order to obtain an M-bit parallel signal, in this case, a 20-times clock pulse is sufficient, due to the provision of five sampling means.