Patents Assigned to Pacific Western Systems, Inc.
  • Patent number: 4820370
    Abstract: The wafer processing boat of a plasma enhanced chemical vapor processor includes an R.F. connector at the inner end of its interleaved electrodes. The R.F. electrical connector includes slidably mated male and female portions for making R.F. electrical connection to the boat through the end wall of the evacuable furnace tube. A particle shield surrounds the mated male and female R.F. connector portions for confinement of particulates released during the mating of the connector. The shield includes an open end which faces downstream of the flow of processing gases to reduce backstreaming of particulates onto the wafers. The electrical male conductors of the connector are covered by a quartz sheath.
    Type: Grant
    Filed: December 12, 1986
    Date of Patent: April 11, 1989
    Assignee: Pacific Western Systems, Inc.
    Inventor: Charles E. Ellenberger
  • Patent number: 4795977
    Abstract: A device tester, such as a memory tester, is electrically interfaced to a device under test, such as a memory die, by means of an improved interface system. The interface system includes an array of coaxial cables for making electrical connection to the test circuits of the device tester by means of coaxial connections at the tester ends. The coaxial cables are fitted at their other ends with slidable two-conductor connector receptacles which make connections to fixed male pins of spring loaded feedthrough connectors passing through a mother board. The spring loaced pins of the feedthroughs make electrical contact to eyelets terminals of strip-line circuits on a probe card (daughter board) terminating on an array of flexible probes for probing the memory die under test. As an alternative, the eyelet terminals of the daughter board are connected to sockets to receive the device under test.
    Type: Grant
    Filed: March 19, 1987
    Date of Patent: January 3, 1989
    Assignee: Pacific Western Systems, Inc.
    Inventors: Keith A. Frost, Timothy Harns, Ronald D. Simmons
  • Patent number: 4761301
    Abstract: In a plasma enhanced chemical vapor processing apparatus first and second sets of electrodes are electrically insulated one from the other via the intermediary of a plurality of insulator bodies. Each of the insulator bodies includes a recessed portion for extending the electrical path length over the surface of the insulator to minimize shorting of the insulators in use. The recess in the insulator body is of generally L-shaped cross section including a radially inwardly directed recessed portion intersecting with an axially directed recess portion. The axially directed portion of the recess is shielded from the plasma discharge, thereby reducing the probability of deposition of conductive material thereon which could otherwise result in shorting of the insulator member. The axial recesses extend into the insulator body from opposite ends thereof.
    Type: Grant
    Filed: August 8, 1986
    Date of Patent: August 2, 1988
    Assignee: Pacific Western Systems, Inc.
    Inventors: Charles E. Ellenberger, Hayden K. Piper
  • Patent number: 4736373
    Abstract: A memory tester for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned, in a first pass, row-by-row and during the first pass scan when the number of failures in any row exceeds the number of spare columns that row is flagged for replacement. Next, in a second pass, the columns of failure data are scanned column-by-column and during the second pass when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. If, during either of the first or second pass, the number of flagged rows or columns, respectively, exceeds a certain number, such as the spare rows or columns, that pass is interrupted and the analysis jumps to the next pass.
    Type: Grant
    Filed: August 3, 1981
    Date of Patent: April 5, 1988
    Assignee: Pacific Western Systems, Inc.
    Inventor: John D. Schmidt
  • Patent number: 4718202
    Abstract: In an apparatus for rounding the edges of semiconductive wafers, the wafers are loaded onto two parallel counter rotating screws one having a right hand thread and the other having a left hand thread. The grooves of respective ones of said screw engage the edges of the semiconductive wafer to be rounded. The grooves of the respective screws are of rounded cross-section and an abrasive slurry is introduced into the grooves to facilitate abrading of the edges of the wafers. A pressure roller engages the edges of the wafers and forces the wafers into the grooves to further facilitate rounding of the edges. Due to the action of the screws, the wafers, as they are being rounded are caused to traverse the length of the screws to provide a continuous processing of the wafers.
    Type: Grant
    Filed: August 23, 1982
    Date of Patent: January 12, 1988
    Assignee: Pacific Western Systems, Inc.
    Inventor: Daniel A. Worsham
  • Patent number: 4661033
    Abstract: Wafers are unloaded from a hot wafer processing boat of the type having a plurality of elongated parallel electrodes defining elongated processing gaps therebetween with the wafers being serially spaced apart lengthwise of the gap. A wafer carrier, into which the wafers are to be unloaded from the hot boat, has elongated receiving means, preferably formed by folds of the wafer carrier, extending lengthwise of the elongated electrodes of the boat. The wafer carrier is positioned over the boat and the boat and the carrier are inverted so that the wafers drop from the hot boat into the receiving means of the wafer carrier. In a preferred embodiment, once the wafers have been unloaded onto the folded wafer carrier, the wafer carrier is unfolded to facilitate access to the wafers.
    Type: Grant
    Filed: August 22, 1984
    Date of Patent: April 28, 1987
    Assignee: Pacific Western Systems, Inc.
    Inventor: Daniel A. Worsham
  • Patent number: 4590422
    Abstract: In an automatic wafer prober, the prober steps through a certain predetermined sequence of die on the wafer. After a certain predetermined number of die have been probed, the prober automatically interrupts the probing sequence and steps the prober off of the wafer onto an abrasive element for scrubbing clean the probe tips. Thereafter, the prober returns to its predetermined probing sequence. The abrasive element is preferably fixidly secured to the wafer chuck. A flat of the abrasive element serves as an alignment flat for registration with a flat of the wafer.
    Type: Grant
    Filed: July 30, 1981
    Date of Patent: May 20, 1986
    Assignee: Pacific Western Systems, Inc.
    Inventor: Vernon C. Milligan
  • Patent number: 4500836
    Abstract: An automatic wafer prober is interfaced with any one of a number of different die testers by storing in memory associated with the wafer prober a plurality of sets of data there being one set of data for each of a plurality of different die testers to be interfaced to the prober. Each set of data defines at least the sense (polarity) of a plurality of test result output signals derived from the particular die tester to be interfaced with the prober. The proper set of stored data is selected by the operator, such as by a digital switch, and a microprocessor employs the selected set of data for modifying the sense of the test result output signals derived from the die tester as fed into the wafer prober so that the die tester output signals as fed into the wafer prober are the same for any one of the plurality of different die tester. In a preferred embodiment, the microprocessor generates a test start signal which is outputted from the prober to the die tester.
    Type: Grant
    Filed: October 31, 1980
    Date of Patent: February 19, 1985
    Assignee: Pacific Western Systems, Inc.
    Inventor: George E. Staudacher
  • Patent number: 4500563
    Abstract: Semiconductive wafers are processed, i.e., etched or layers deposited thereon, by means of a plasma enhanced chemical vapor processing system wherein the plasma is generated by a train of R.F. power pulses. The pulse repetition rate, pulse length and peak power level of the individual pulses are independently variably controlled to variably control the uniformity of the processing of the semiconductive wafers within the processing gaps.
    Type: Grant
    Filed: December 15, 1982
    Date of Patent: February 19, 1985
    Assignee: Pacific Western Systems, Inc.
    Inventors: Charles E. Ellenberger, George L. Bower, William R. Snow
  • Patent number: 4460997
    Abstract: A memory tester is disclosed for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned first by row and when the number of failures in any row exceeds the number of spare columns that row is flagged for replacement. Next, the columns of failure data are scanned and when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. During the scan of the columns, previously flagged rows are masked such that failures which are to be repaired are not counted.
    Type: Grant
    Filed: July 15, 1981
    Date of Patent: July 17, 1984
    Assignee: Pacific Western Systems Inc.
    Inventor: Timothy Harns
  • Patent number: 4460999
    Abstract: A memory tester is disclosed for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix under address control of a programmable pattern generator to derive failure data and stores the failure data in corresponding rows and columns in a second memory matrix. Failure data in the second memory is scanned by an error analysis circuit, under control of the pattern generator, first by row and when the number of failures in any row exceed the number of spare columns that row is flagged for replacement. Next, the columns of failure data are scanned and when the number of failures in any column exceeds the number of spare rows, that column is flagged for replacement. During the scan of the columns, previously flagged rows are masked such that failures which are to be repaired are not counted.
    Type: Grant
    Filed: July 15, 1981
    Date of Patent: July 17, 1984
    Assignee: Pacific Western Systems, Inc.
    Inventor: John D. Schmidt
  • Patent number: 4292722
    Abstract: In a lead screw drive, such as that used in a lightweight lathe or milling machine for driving the workpiece relative to the cutting tool, the core of a drive nut is made of a material having a relatively low melting temperature, such as babbitt metal or a relatively rigid thermoplastic material. The low melting point material is contained within a nut housing as of steel. The openings in the nut housing for passage of the lead screw are scaled in a fluid type relation by means of elastic sealing members as of silicone rubber having a melting point above that of the relatively low melting point core portion of the nut. An electrical heating cartridge element is contained within the nut housing in good thermally conductive relation with the low melting point core material.
    Type: Grant
    Filed: August 13, 1979
    Date of Patent: October 6, 1981
    Assignee: Pacific Western Systems, Inc.
    Inventor: Daniel A. Worsham
  • Patent number: 4251772
    Abstract: In a probe head for an automatic semiconductive wafer prober, the probe head includes a probe body means for coupling the probe head to the probe holder surrounding a chuck which carries the wafer. The chuck is moveable in the plane of the wafer (horizontal) and orthogonal to the plane of the wafer (vertical) for sequentially moving a pattern of probe heads into testing engagement with corresponding patterns of test points on the wafer under test. The probe head includes a testing head having a probe portion (blade, needle or point) for making electrical contact with a respective test point on the wafer. The test head is coupled to the probe body by means of a way for guiding the initial vertical adjustable movement of the testing head in the vertical direction, whereas the probe body is pivotably and slideably coupled to the probe holder so as to permit a second initial adjustment of the probe body in the horizontal plane for establishing the test probe pattern.
    Type: Grant
    Filed: December 26, 1978
    Date of Patent: February 17, 1981
    Assignee: Pacific Western Systems Inc.
    Inventors: Daniel A. Worsham, Jack E. Ashley, Joseph M. Munoz
  • Patent number: 4249846
    Abstract: In a rotary vacuum sealed wafer transport system for transporting semiconductive wafers between ambient atmosphere and subatmospheric pressure within a wafer processing station, the wafers, on a conveyor web pass through a slot in the vacuum chamber of the processing station. The evacuable envelope of the processing station has an external concave face portion intersecting with a generally planar face portion with the slot being positioned generally at the intersection of the concave and planar face portions. A deformable elastic roller, preferably pneumatically inflated, is disposed for rolling sealing engagement with the conveyor web and wafer and for wiping sealing engagement with portions of the planar and concave faces to provide a gas tight seal of the slot while permitting passage of the conveyor web with the wafers thereon into the evacuated wafer processing station. In a preferred embodiment, the conveyor web passes through input and output slots with pneumatic rollers sealing the pair of slots.
    Type: Grant
    Filed: December 20, 1978
    Date of Patent: February 10, 1981
    Assignee: Pacific Western Systems, Inc.
    Inventor: Daniel Worsham