Abstract: A conditioner unit is wired in parallel with a pair gain test controller used to test a digital loop carrier telephone network. The conditioner unit senses a signal intended to request test results from the pair gain test controller and provides a response signal which indicates that the pair gain test controller performed a successful test, even though the pair gain test controller was not activated. This allows testing of the network without use of a bypass pair or the need to interface the digital loop carrier network with the pair gain test controller.

Abstract: A conditioner unit is wired in parallel with a pair gain test controller used to test a digital loop carrier telephone network. The conditioner unit senses a signal intended to request test results from the pair gain test controller and provides a response signal which indicates that the pair gain test controller performed a successful test, even though the pair gain test controller was not activated. This allows testing of the network without use of a bypass pair or the need to interface the digital loop carrier network with the pair gain test controller.

Abstract: A conditioner unit is wired in parallel with a pair gain test controller used to test a digital loop carrier telephone network. The conditioner unit senses a signal intended to request test results from the pair gain test controller and provides a response signal which indicates that the pair gain test controller performed a successful test, even though the pair gain test controller was not activated. This allows testing of the network without use of a bypass pair or the need to interface the digital loop carrier network with the pair gain test controller.

Abstract: A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.

Abstract: A monolithic integrated circuit amplifier has a gain stage and a buffer stage. The buffer stage includes an output stage and two separate voltage supplies, the second of which has a greater magnitude than the first. Switching circuitry is included that is connected to the output stage via a regulator bus. When an output demand voltage is less than a switch-over threshold, current to the output stage is provided substantially entirely from the first voltage supply; when the output demand voltage is greater than the switch-over threshold, current to the output stage is provided substantially entirely from the second voltage supply. Collector voltage at the output stage can be maintained greater than the emitter voltage by a predetermined, substantially constant amount.

Abstract: The invention provides a stable voltage reference circuit that has a single reference diode junction. Two separate current sources are switched so as to alternately apply a first and second current to the junction, with the second current being larger than the first. The voltage over the junction thereby alternates between a first AC input voltage (V1) that has a positive temperature dependence (dV1/dT) and a second AC input voltage (V2) that has a negative temperature dependence (dV2/dT). Combining circuitry is included for adding the first and second input voltages and for thereby generating an output voltage (Vref) substantially constant with absolute temperature. The combining circuitry preferably includes an amplifier that has, for the first input voltage, a gain substantially equal to the ratio of the negative temperature dependence divided by the positive temperature dependence.

Abstract: A flash converter is preceded by an accurate continuous-time error amplifier operating on the difference between the input signal and a feedback DAC. The DAC output is operatively coupled to the amplifier input virtual ground or summing node through, for example, a set of precision capacitors. The input circuit is also coupled to the amplifier input through a continuous-time element such as a set of precision capacitors, approximately equal in capacitance to those coupled to the DAC. The amplifier may have a moderate closed-loop forward gain such as 16 with a high-pass characteristic beyond, for example, 10 Hz. The DAC is controlled by the latched output of a digital signal processing block, which uses digital outputs from the flash converter and the last latched output to predict the next value of the input signal. Converter control loop stability is afforded by providing a lowpass character to the prediction circuit.

Abstract: A improved method for optimally equalizing a multicarrier communications system in the presence of both intersymbol interference (ISI) and colored noise. The method provides a frequency-domain training algorithm to obtain a minimum mean square error (MMSE) equalizer that accounts for both intersymbol interference (ISI) and colored noise, maximizes the signal to noise ratio (SNR) of systems using Discrete Multitone (DMT) modulation, and results in significant performance gains over prior equalization methods.

Abstract: A coordinated timing technique is disclosed which allows a single analog-to-digital converter (ADC) to be timeshared by multiple digital transceivers operating on independent subscriber loops with independent sampling phase requirements. The multiple transceivers must all operate from a single master reference clock. However, any arbitrary timing phase relationship between the transceivers can be accommodated.

Abstract: The invention provides a stabilized power converter having an input voltage and an output voltage, where the stabilized converter operates similar to a conventional converter under normal conditions, and operates continuously at the maximum power transfer point during overload conditions. The stabilized converter comprises a voltage control loop for regulating output voltage, and a stabilization loop for regulating input voltage. In a preferred embodiment, the stabilization loop senses the input voltage to the stabilized converter and compares it to a reference voltage. Whenever converter input voltage is above the maximum power transfer voltage, no action is taken by the stabilization loop, and the converter operates in the conventional manner. As converter input voltage approaches the maximum power transfer voltage, converter output voltage and corresponding converter input and output power are reduced to compensate.

Abstract: A frequency synthesizer for producing an output whose phase and/or frequency can be finely adjusted under digital control. The synthesizer utilizes a phase lock loop including a phase detector responsive to a prescale divide-by-N frequency divider and a feedback divide-by-M frequency divider to product an output signal F.sub.OUT. The phase of F.sub.OUT can be shifted by a small increment by slightly adjusting the values of the divisors M and N.

Abstract: A digital-to-analog converter (DAC) is disclosed which uses an oversampled modulation technique followed by an analog lowpass filter to generate an output waveform with four precisely controlled amplitude levels for 2B1Q data transmission applications. The DAC accepts a 2-bit input word at the baud rate and generates one of four possible analog output amplitudes having relative ratios of +3, +1, -1, and -3.