Abstract: A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n? type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.

Abstract: In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p?type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch.

Abstract: After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n? buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n? buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n? buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

Abstract: An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

Abstract: A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1×, 2×, and 4×, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Abstract: A trenched, vertical MOS-gated switch is described that uses only three or four masking steps to fabricate. In one embodiment, one mask is used to form first trenches having a first depth, wherein the first trenches are filled with doped polysilicon to form gates to control the conduction of the switch. A second mask is used to form second trenches having a shallower second depth. The second trenches are filled with the same metal used to form the top source electrode and gate electrode. The metal filling the second trenches electrically contacts a top source layer and a body region. A third mask is used to etch the metal to define the source metal, the gate electrode, and floating rings in a termination region surrounding the active area of the switch. An additional mask may be used to form third trenches in the termination region that are deeper than the first trenches.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

Abstract: A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? drift layer, a p-well, trenched insulated gates formed in the p-well, and n+ regions between at least some of the gates, so that vertical npn and pnp transistors are formed. A cathode electrode is on top, and an anode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the cathode electrode. To direct high energy electrons away from a gate oxide layer on the sidewalls of the trenches, boron is implanted between the trenches so p+ regions are formed in the mesas of the less-doped p-well. The p+ regions break down during an over-voltage event before the p-well breaks down in the mesas.

Abstract: A lateral insulated gate turn-off device includes an n-drift layer, a p-well formed in the n? drift layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, a trenched first gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, an anode electrode electrically contacting the p+ type anode region, and a trenched second gate extending from the p+ type anode region into the n-drift layer. For turning the device on, a positive voltage is applied to the first gate the reduce the base width of the npn transistor, and a negative voltage is applied to the second gate to effectively extend the p+ emitter of the pnp transistor further into the n-drift layer to improve performance.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

Abstract: An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n? layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. After forming the p-well, boron ions are implanted into the exposed surface of the p-well to form a p+ region. The n-epi layer is then grown over the p-well and the p+ region, and the boron in the p+ region is diffused upward into the n-epi layer and downward to form an intermediate p+ region. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter) and the overall dopant concentration and thickness of the p-type base to optimize the thyristor's performance.

Abstract: A vertical bidirectional insulated gate turn-off (IGTO) device includes a top half formed over a top surface of a substrate and a bottom half formed over the bottom surface of the substrate. A top electrode is formed over the top half, and a bottom electrode is formed over the bottom half. The layered structure forms vertical NPN and PNP transistors. Each half includes trenched gates. When a first polarity voltage is applied across the electrodes, one of the halves may be turned on by biasing its gates to conduct current between the top and bottom electrodes. When a voltage of an opposite polarity is applied across the electrodes, the other one of the halves may be turned on by biasing its gates to conduct current between the two electrodes. In one embodiment, biasing the gates increases the beta of the NPN transistor to turn on the device.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N? epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. To speed up the removal of residual electrons in the p-well after the gate electrode voltage is removed, a p+ region is added adjacent the n+ regions, and an n-layer is added below the p+ region. The cathode electrode directly contacts the p+ region and the n+ regions. During turn-off, the p+ region provides holes which recombine with the residual electrons to rapidly terminate the current flow.