Abstract: A pre-designed system-on-chip architecture and method includes several standard library devices, HDL source code, simulation environment and regression, synthesis scripts, software header files, software libraries, ASIC verification test suites, and makefiles. The standard library devices comprise an integrated CPU, a shared memory controller, a peripheral controller, system peripherals, a DMA controller, embedded memory, and general system control. CPU bridges are used to accommodate a variety of processor types and to insulate users from the complexities of interfacing to different kinds of processors. Such CPU bridges further allow the latest processors to be rapidly integrated into existing integration platforms and designs.

Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) and the DMA peripheral(s) using a Memory Access Controller (MAC) and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.

Abstract: A interrupt controller includes specialized interfaces and controls for ARM7TDMI-type microcontroller cores. Such sends interrupt vectors and IRQ or FIQ interrupt requests to the processor depending on particular interrupts received. Wherein, THUMB program execution is more economical with program code space, and an interrupt service routine preamble is coded in ARM program code to cause a switch to THUMB program execution. The interrupt service routine preamble is shared amongst all the interrupt service routines to further economize on program code space.

Abstract: The System-on-Chip (SOC) interconnection apparatus and system discloses an internal switching fabric that interconnects, via standard connection ports, one or more requestors and one or more addressable targets on a single semiconductor integrated circuit. Each target has a unique address space, may or may not have internal arbitration, and may be resident (i.e., on-chip) memory, a memory controller for resident or off-chip memory, an addressable bridge to a device, system, or subsystem, or any combination thereof. Targets and requesters are connected to the internal switching fabric using target and requestor connection ports. The internal switching fabric routes signals between requesters and targets using one or more decoder/router elements that determine which target is the designated target using an internal system memory map. Dedicated arbiters may be included for targets without internal arbitration.

Abstract: An ATA/IDE host controller 100 generated from an HDL design base and a default frequency configuration script is disclosed. The controller supports ATA/IDE interface communications at a user-selected default frequency of 33, 66, 100, or 133 Mhz and at frequencies other than the default frequency using a set of programmable override timing registers 121. An internal timing control module 110 provides either the default timing parameters or the override timing parameters to the IDE host interface 102, according to the programmable override control 301.

Abstract: A system resource router interfaces initiators through protocol-adapting sockets to a plurality of sub-buses. A switch matrix allows at least some of the sockets to be connected to two or more of the sub-buses. Each sub-bus interfaces through a channel controller to target devices like memory and peripherals. A graphical user interface, assembly program, and computer-aided design platform allow users to customize system resource router configurations for particular applications. At least one embodiment produces Verilog or other hardware description language intellectual property technology libraries. It implements the optimal mix of sub-buses, switches, sockets, and controllers that will be needed for a particular user application.

Abstract: The System-on-Chip apparatus and integration methodology disclosed includes a single semiconductor integrated circuit having one or more processor subsystems, one or more DMA-type peripherals, and a Memory Access Controller (MAC) on a first internal unidirectional bus. The first internal unidirectional bus controls transactions between the processor subsystem(s) the MAC, and the DMA peripheral(s) using a single centralized address decoder and unidirectional, positive-edge clocked address and transaction control signals. The first internal unidirectional bus can support burst operation, variable-speed pipelined memory transactions, and hidden arbitration. The SoC may include a second internal unidirectional bus that controls transactions between the processor subsystem(s) and non-DMA peripherals. The second internal unidirectional bus controls transactions between the processor subsystem(s) and the non-DMA peripheral(s) using unidirectional address and transaction control signals.

Abstract: An SOC architecture that provides a latency tolerant protocol for internal bus signals is disclosed. The SOC includes at least a processor core and one or more peripherals that communicate on a first internal bus that carries signals having a latency tolerant signal protocol that enables an arbitrary number of pipeline stages between any signal initiator and any signal target. A shared memory subsystem, DMA-type peripherals, and a second internal bus with a topology overlapping the first bus, may also be included. All signals over both busses are point-to-point and registered and all transactions on both busses are handshaked. An arbitrary number of flip-flops, multiplexing routers, and/or decoding routers may be included between any signal initiator and any signal target on either bus, and may be added at any time during the design and layout of the SOC.

Abstract: A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.

Abstract: An on-the-fly error detection and correction hardware core for a mass storage hard disk drive comprises a microcode machine optimized and limited to doing Galois Field arithmetic (GF[2.sub.8 ]) in support of Reed-Solomon error detection and correction (RS-EDC). The microcode machine is implemented as a hardware core in a system-on-a-chip design that includes a general purpose core RISC-processor. A dual-input arithmetic logic unit (ALU) includes a set of basic arithmetic blocks necessary to support the RS-EDC operations, i.e., a multiplier, a dedicated adder, a general purpose adder, a divider, a log unit, a quadratic solution lookup, a cubic solution lookup, and a move datapath. The operations and outputs of all the basic arithmetic blocks are presented in parallel to an op-code selector. The selected output is routed back for deposit to one of eight general purpose registers (R0-R7).