Patents Assigned to PANASONIC INTELLECTUAL PROPRETY MANAGEMENT CO., LTD.
  • Patent number: 10978367
    Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPRETY MANAGEMENT CO., LTD.
    Inventors: Chiaki Kudou, Takashi Hasegawa, Kouichi Saitou
  • Patent number: 10830652
    Abstract: A stress measurement device includes a first obtaining unit obtaining thermal data including information indicating a temperature of a measuring region, a second obtaining unit obtaining data related to stress occurring in one part of the measuring region, and a controller finding stress occurring in the measuring region from the thermal data and the data related to the stress. The controller finds, first waveform data respectively on the one part and a part other than the one part based on a change with time of the thermal data, and second waveform data based on a change with time of the data related to the stress. The controller finds, disturbance data through a deduction of the second waveform data from the first waveform data on the one part, and stress data indicating stress occurring in the part through a deduction the disturbance data from the first waveform data on the part.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 10, 2020
    Assignee: PANASONIC INTELLECTUAL PROPRETY MANAGEMENT CO., LTD.
    Inventor: Yousuke Irie
  • Patent number: 10763550
    Abstract: Provided is a stacked all-solid-state battery including a plurality of all-solid-state batteries, each all-solid-state battery including a cathode layer that has a cathode current collector and a cathode active material layer containing a cathode active material and formed on the cathode current collector, an anode layer that has an anode current collector and an anode active material layer containing an anode active material and formed on the anode current collector, and a solid electrolyte layer disposed between the cathode active material layer and the anode active material layer and containing a solid electrolyte having a lithium ion conductivity. The plurality of all-solid-state batteries are stacked, and the plurality of all-solid-state batteries include two adjacent all-solid-state batteries, the two all-solid-state batteries being configured such that the cathode current collector of one all-solid-state battery is directly joined to the anode current collector of the other all-solid-state battery.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 1, 2020
    Assignee: PANASONIC INTELLECTUAL PROPRETY MANAGEMENT CO., LTD.
    Inventors: Kenta Hasegawa, Takao Kuromiya