Patents Assigned to PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
  • Patent number: 10854744
    Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 1, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
  • Patent number: 10848145
    Abstract: A driver circuit which is supplied with a positive power supply voltage, a negative power supply voltage, and an input signal, and drives a switching element including a control terminal according to the input signal includes: a first output terminal connected to the control terminal via a first impedance circuit, and outputs the positive power supply voltage or the negative power supply voltage according to the input signal, to charge the control terminal and put the switching element into an ON state; a negative power supply terminal supplied with the negative power supply voltage; a negative voltage switch having a first end connected to the negative power supply terminal; a third output terminal connected to a second end of the negative voltage switch and to the control terminal via a second impedance circuit; and a first discharge switch disposed between the negative power supply terminal and the first output terminal.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 24, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Takuya Ishii, Yoshihito Kawakami, Takahiro Uehara, Ginga Katase
  • Patent number: 10847610
    Abstract: In a semiconductor device including first and second conductive plates (FFPs) formed by being stacked in layer, the first conductive plate and the second conductive plate include linear regions elongated to face each other along a longitudinal direction in which a length with which source region and drain region elongated in parallel face each other is longest, and are elongated in a short-side direction orthogonal to the longitudinal direction. Here, high voltage wiring of either one of source wiring and drain wiring is elongated in the short-side direction to intersect the linear regions of the first conductive plate and the second conductive plate, and low voltage wiring of the other one of source wiring and drain wiring is elongated in the short-side direction to intersect at least one linear region of the first conductive plate or the second conductive plate.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: November 24, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Teruhisa Ikuta, Hiroshi Sakurai, Satoru Kanai
  • Patent number: 10847556
    Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: November 24, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Makoto Ikuma, Hiroyuki Amikawa, Takayasu Kito, Shinichi Ogita, Junichi Matsuo, Yasuyuki Endoh, Katsumi Tokuyama, Tetsuya Abe
  • Patent number: 10847702
    Abstract: A semiconductor module includes: a semiconductor element; a wiring substrate on which the semiconductor element is mounted; a heat dissipation substrate; a first metal material that bonds the wiring substrate and the heat dissipation substrate; and a second metal material that bonds the wiring substrate and the heat dissipation substrate and has a different melting point from the first metal material. Each of the following is at least partially bonded: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, the second metal material and the wiring substrate, the second metal material and the heat dissipation substrate, and the first metal material and the second metal material. Each of the following is bonded by alloying: the first metal material and the wiring substrate, the first metal material and the heat dissipation substrate, and the first metal material and the second metal material.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: November 24, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Takeshi Kawabata, Kiyomi Hagihara, Takashi Yui, Naofumi Koga
  • Publication number: 20200365771
    Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a first layer in contact with the first electrodes of the semiconductor element and a second layer located on a side opposite to the first electrodes, an average crystal grain size of crystals included in the first layer is larger than an average crystal grain size of crystals included in the second layer, and the second layer is spaced apart from the first electrodes of the semiconductor element.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 19, 2020
    Applicants: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD., PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Masanori HIROKI, Shigeo HAYASHI, Kenji NAKASHIMA, Toshiya FUKUHISA, Keimei MASAMOTO, Atsushi YAMADA
  • Patent number: 10794848
    Abstract: A gas sensor includes a first electrode having a first main surface and a second main surface opposite to the first main surface; a second electrode having a third main surface facing the second main surface and a fourth main surface opposite to the third main surface; a metal oxide layer disposed between the first electrode and the second electrode, and being in contact with the second main surface and the third main surface; and an insulating film covering at least a part of the first electrode, a part of the second electrode, and at least a part of the metal oxide layer. At least a part of the fourth main surface is exposed to gas which contains a gas molecule including a hydrogen atom. A resistance value of the metal oxide layer decreases when the second electrode is in contact with the gas molecule.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 6, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Kazunari Homma, Zhiqiang Wei
  • Patent number: 10785430
    Abstract: A solid-state imaging device includes: a pixel including a photoelectric converter that generates a charge and a charge accumulator that converts the charge into a voltage; a controller that causes the pixel to perform exposure in a first exposure mode and convert the charge into the voltage with a first gain to output a first pixel signal, and causes the pixel to perform exposure in a second exposure mode and convert the charge into the voltage with a second gain to output a second pixel signal, the second exposure mode being shorter in exposure time than the first exposure mode, and the second gain being lower than the first gain; and a signal processor that synthesizes the second pixel signal after amplification and the first pixel signal.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 22, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Makoto Ikuma, Takahiro Muroshima, Takayasu Kito, Hiroyuki Amikawa, Tetsuya Abe
  • Patent number: 10778921
    Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 15, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Yutaka Abe, Kazuko Nishimura, Hiroshi Fujinaka, Masahiro Higuchi, Dai Ichiryu
  • Patent number: 10777711
    Abstract: A light emitting device includes a wavelength conversion element, and an excitation light source which radiates excitation light to the wavelength conversion element. The wavelength conversion element includes a support member having a supporting surface, and a wavelength conversion member disposed on the supporting surface so as to be contained within the support member when the support member is viewed from the supporting surface side. An outer peripheral region on the support member, which is an outer peripheral portion of an arrangement region including the wavelength conversion member and is exposed from the wavelength conversion member, includes a light absorbing portion which can absorb first light having same wavelength as the excitation light or a light scattering portion which can scatter the first light. The arrangement region includes a reflective member which is disposed between the wavelength conversion member and the support member, and is different from the support member.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: September 15, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Kazuhiko Yamanaka, Hideki Kasugai, Hirotaka Ueno, Kimihiro Murakami
  • Patent number: 10756165
    Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 25, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Kouki Yamamoto, Masatoshi Kamitani, Shingo Matsuda, Hiroshi Sugiyama, Kaname Motoyoshi, Masao Nakayama
  • Patent number: 10756172
    Abstract: A semiconductor device having a silicon-on-insulator (SOI) structure in which a source region and a drain region extend along a longitudinal direction that is a direction along a longer side of sides facing each other, and are disposed side-by-side in a lateral direction that is a direction perpendicular to the longitudinal direction. In a plan view, a body region extends along the longitudinal direction and is surrounded by a drift region and an insulating region. A space between the insulating region and the body region in the lateral direction becomes narrower from the center to the end of the body region in the longitudinal direction. This achieves high breakdown voltage in the semiconductor device.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: August 25, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Teruhisa Ikuta, Hiroshi Sakurai, Satoru Kanai
  • Patent number: 10742675
    Abstract: Provided is a fraudulent message detection device that detects a fraudulent message in a bus network and includes: a resynchronization detector that detects an edge of a signal on a bus in the bus network and determines whether to perform resynchronization, so as to adjust a sampling point in a one-bit period; a transmission and receiving control unit that obtains a first logical value and a second logical value in a one-bit period after the resynchronization detector determines to perform the resynchronization, the first logical value being a logical value at a sampling point used before the edge is detected, the second logical value being a logical value at a sampling point after the resynchronization is performed; a comparator that compares the first and second logical values; and a fraud detection processing unit that executes post-fraud-detection processing, when the first and second logical values do not coincide.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 11, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventor: Makoto Fujiwara
  • Patent number: 10741545
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 11, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Masaki Tamaru, Kazuma Yoshida, Michiya Otsuji, Tetsuyuki Fukushima
  • Patent number: 10742906
    Abstract: A solid-state imaging device includes: a pixel array unit in which a plurality of pixels are arranged in rows and columns; a plurality of column signal lines which are provided in one-to-one correspondence with pixel columns; a column processor including a plurality of column AD circuits provided in one-to-one correspondence with the plurality of column signal lines; a power supply variation detector which is connected to a power supply wire through which a power supply voltage is transmitted to each of the pixels, and which detects, in correspondence with pixel rows, power supply variation components attributed to variations in the power supply voltage; and a power supply variation corrector which corrects, for each of the pixel rows, a pixel signal detected by the column processor, using the power supply variation components detected by the power supply variation detector.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 11, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Makoto Ikuma, Takahiro Muroshima, Takayasu Kito, Hiroyuki Amikawa, Tetsuya Abe