Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
Type:
Grant
Filed:
February 2, 2016
Date of Patent:
October 3, 2017
Assignee:
PANNOVA SEMIC, LLC
Inventors:
Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato
Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.
Type:
Grant
Filed:
November 28, 2012
Date of Patent:
March 15, 2016
Assignee:
Pannova Semic, LLC
Inventors:
Tsutomu Oosuka, Hisashi Ogawa, Yoshihiro Sato