Abstract: This application is directed to sensing touch events on a touch sensing panel including a capacitive sensor array. The capacitive sensor array includes a plurality of touch sensing regions and is coupled to a processing device. The processing device identifies, and generates drive signals for, the touch sensing regions of the touch sensing panel. Each drive signal corresponds to a distinct touch sensing region and includes a respective train of periodic pulses. For each drive signal, the respective train of periodic pulses has a respective phase offset with respect to a reference (e.g., a train of periodic pulses of one of the plurality of drive signals, a fixed reference time). While applying the drive signals on the touch sensing regions, the processing device measures capacitance sensing signals from the touch sensing regions. Touch events are detected on the capacitive sensor array based on the capacitance sensing signals.

Abstract: An electronic device includes a capacitive sense array made of a plurality of sense electrodes. A subset of sense electrodes of the capacitive sense array is scanned to obtain a plurality of capacitive sense signals, and a touch map is generated from at least a subset of the capacitive sense array based on the plurality of capacitive sense signals. The electronic device determines that the touch map corresponds to a passive stylus. In accordance with a determination that the touch map corresponds to the passive stylus, the electronic device determines a stylus position and one or more orientation parameters of the passive stylus with respect to a surface of the capacitive sense array. In some embodiments, a stylus parameter determination model is applied to process the touch map and determine at least the one or more orientation parameters of the passive stylus.

Abstract: This application is directed to controlling an electrical idle state of a retimer of a data communication channel. A receiving side of the retimer obtains an input signal including at least an exit command and a data sequence following the exit command. The exit command requests the retimer to exit a target energy saving state and transmit the data sequence. The retimer splits the input signal into two distinct signals including a control signal carrying the exit command and a data signal carrying the data signal. The retimer extends the exit command carried by the control signal, outputs the control signal carrying the extended exit command at an output of the retimer, and in accordance with a determination that the retimer has been equalized and locked, outputs the data signal carrying the data sequence at the output of the retimer.

Abstract: An electronic device (e.g., a CTLE circuit of a receiver of a data link) includes a current source and two differential transistor groups. The current source is configured to generate a bias current according to a data rate of data carried by a pair of differential input signals. A subset of the two differential transistor groups is configured to be driven by the bias current to generate a pair of differential output signals from the pair of differential input signals. The two differential transistor groups include a first plurality of transistors receiving a first input signal and a second plurality of transistors receiving a second input signal. The first and second input signals form the pair of differential input signals. In some implementations, each transistor is coupled to a biasing circuit including a DC path coupled to an adjustable biasing voltage level for selecting and deselecting the respective transistor.

Abstract: This application is directed to controlling a low power mode of a data communication channel. An electronic device includes an input interface for receiving an input signal. A signal conditioning circuit is coupled to the input interface, and configured to be disabled and consume power below a first threshold power level in a low power mode. A first signal detector is coupled to the signal conditioning circuit, and a second signal detector is coupled to the first signal detector. The first signal detector is configured to monitor a differential mode component of the input signal for controlling the signal conditioning circuit to exit the low power mode. The second signal detector is configured to, in the low power mode, detect a start of the input signal and enable the first signal detector based on a common mode component of the input signal.

Abstract: This application discloses adaptively setting feed-forward equalization (FFE) for a data communication channel. An equalization signal is generated using a finite impulse response (FIR) filter that has a plurality of FIR coefficients configured to be defined by one of a plurality of preset configurations. A lookup table has a plurality of rows, and each row is associated with a different preset configuration of the FIR coefficients and identifies a subset of respective preset configurations corresponding to a subset of FIR coefficients. In some implementations, a temporal sequence of preset configurations of the FIR coefficients is selected from the lookup table, until a predefined equalization criterion is satisfied. In some implementations, residual errors are determined and correspond to signal samples of the equalization signal, and a sequence of preset configurations of the FIR coefficients is selected from the lookup table based on the residual errors.

Abstract: This application is directed to a data interface having an input interface for receiving a differential input signal and a reference interface for providing a predefined reference voltage. A high pass filter is coupled to the input interface, and configured to filter the differential input signal and generate a filtered differential input signal. A differential integrator is coupled to the high pass filter and reference interface, and configured to receive the filtered differential input signal and generate a differential output signal including a first output signal and a second output signal. Each of the first and second output signals has a common mode output voltage substantially equal to the predefined reference voltage. In some embodiments, the data interface includes a connector including a plurality of data lanes and a pair of command pins that are distinct from the data lanes and coupled to the input interface.

Abstract: A driver device of a data interface includes an input/output (I/O) interface, a power interface, a transmitter circuit, and a switching unit. The I/O interface is configured to couple to a load device. The power interface is configured to provide a power supply for transmitting data via the I/O interface. The transmitter circuit is coupled to the I/O interface and to the power interface and is configured to be powered by the power supply and provide an output signal to the load device via the I/O interface in a transmitter mode. The switching unit is coupled to the power interface and is configured to switch off the power interface for the transmitter circuit when the transmitter circuit is operating in a low power state. The transmitter circuit has a power consumption level below a threshold power level in the low power state.

Abstract: A method controls duty cycle distortion of clock signals. An electronic device obtains an input clock signal having a first frequency and a sampling clock signal having a second frequency that is lower than the first frequency. The sampling clock signal has a random noise distribution. The sampling clock signal is applied to sample high voltage duty cycles and low voltage duty cycles of the input clock signal for a duration of time to obtain a sampling result. The electronic device determines a duty cycle distortion level of the input clock signal in the duration of time based on the sampling result. A duty cycle control signal is generated based on the duty cycle distortion level to control the high voltage duty cycles of the input clock signal.

Abstract: This application is directed to frequency controlling in an electronic device that includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller identifies a temporal range including a peak instant at which the second reference signal reaches a peak frequency, select a switching instant within the temporal range based on a known temporal position of the peak instant with respect to the temporal range, and control the selector to select the second reference signal as the input signal at the switching instant.

Abstract: This application is directed to frequency controlling in an electronic device (e.g., a retimer of a data link). The electronic device includes a selector, a clock generated, and a controller. The selector selects one of a first reference signal and a second reference signal as an input signal having an input phase. The clock generator receives the input signal and generates a periodic signal with reference to the input signal, and the periodic signal has an output phase that matches the input phase of the input signal. While the first reference signal is selected as the input signal, the controller determines whether the second reference signal is in a temporal range in which the second reference signal reaches a peak frequency and controls the selector to select the second reference signal as the input signal in accordance with a determination that the second reference signal is in the temporal range.

Abstract: Controlling Duty Cycle Distortion with a Mixed-Signal Circuit A method controls the duty cycle distortion of clock signals. An electronic device obtains an input clock signal and generates a first output voltage and a second output voltage from the input clock signal. The first output voltage has a first direct current (DC) voltage level indicating, in real time, a first duty cycle length of high voltage duty cycles of the input clock signal. The second output voltage has a second DC voltage level indicating, in real time, a second duty cycle length of low voltage duty cycles of the input clock signal. The difference between the first and second DC voltage levels corresponds to the duty cycle distortion level of the input clock signal. A duty cycle control signal is generated based on the difference between the first and second DC voltage levels to control the high voltage duty cycles of the input clock signal.

Abstract: This application is directed to a capacitive sense array including a two-dimensional array of capacitive sense elements. Each capacitive sense element is formed by a respective intersection of (i) a respective row electrode in a first electrode layer and (ii) a respective column electrode in a second electrode layer. Each column of the capacitive sense elements includes two or more interdigitated column electrodes. Each row electrode forms two or more rows of capacitive sense elements at intersections with the column electrodes.

Abstract: This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. The data link is initiated with the full data path and a first sequence of data packets is transferred via the full data path in accordance with a low data rate setting. While transferring the first sequence of data packets, the first sequence of data packets is manipulated in the full data path to establish a connection of the data link, and in response to establishing the connection of the data link, the data link is switched from the full data path to the bit level data path.

Abstract: An electronic device has a display substrate including a display area, a driver area, and a fan-out area. The fan-out area has interconnects providing electrical accesses to display elements of the display area. The device has a driver chip disposed on the driver area. The driver chip includes a first edge adjacent to the display area and multiple pad groups, each pad group including a respective row of electronic pads that is (i) arranged substantially in parallel with the first edge and (ii) electrically coupled to a respective subset of display elements via respective interconnects routed on a respective region of the fan-out area. The pad groups include a first pad group and a second pad group. The first and second pad groups have two different distances from the first edge and correspond to two different subsets of interconnects routed on two non-overlapping regions of the fan-out area.

Abstract: An electronic device has a display screen and a driver chip disposed on a driver area of the display screen. A fan-out area of the display screen has interconnects configured to provide electrical accesses to display elements of the display area. The driver chip includes a first edge, a second edge, and a row of electronic pads proximate to the first edge. The electronic pads have a first subset of end pads at a first end of the first row, a second subset of end pads at a second opposite end of the first row, and a subset of intermediate pads located between the first subset and second subset of end pads. The first subset of end pads physically contact a first subset of interconnects from the first edge, and the subset of intermediate pads physically contact a second subset of interconnects from the one or more second edges.

Abstract: Touch events are detected on a touch sensing surface coupled to a capacitive sense array and one or more force electrodes. During a plurality of scan cycles, a plurality of capacitive sense signals and one or more force signals are obtained from capacitive sense electrodes of the capacitive sense array and the one or more force electrodes, respectively, and applied to determine a temporal sequence of touches on the touch sensing surface. For each touch of the temporal sequence of touches, a touch location on the touch sensing surface is identified based on the capacitive sense signals, and a force value associated with force applied at the touch location is determined based on the force signals. A gesture associated with the temporal sequence of touches is thereby identified based on the touch locations and the force values of the temporal sequence of touches.

Abstract: This application is directed to detecting touch events on a touch sensing surface coupled to a capacitive sense array and one or more force electrodes. The capacitive sense array includes a plurality of sense electrodes configured to provide a plurality of capacitive sense signals. The force electrodes are configured to provide one or more force signals. A subset of sense electrodes are determined to be associated with a candidate touch based on the capacitive sense signals and their associated baseline values. When force associated with the force signals is below a predetermined force threshold, the candidate touch is determined as an invalid touch (e.g., coverage by a water drop on an area of the touch sensing surface corresponding to the subset of sense electrodes). Baseline values are adjusted for the subset of sense electrodes for determining subsequent touch events associated with the subset of sense electrodes.

Abstract: This application is directed to detecting touch events on a touch sensing surface coupled to a capacitive sense array and one or more force sensors. The capacitive sense array includes a plurality of sense electrodes configured to provide a plurality of capacitive sense signals. The force sensors are configured to provide one or more force signals. In accordance with the plurality of capacitive sense signals, one or more candidate touches are determined on the touch sensing surface, and used to determine an expected force shape. An actual force shape caused on the touch sensing surface by the candidate touches is determined from the one or more force signals. The actual and expected force shapes are compared to determine magnitudes of force associated with each of the one or more touch candidates, thereby determining whether each of the one or more candidate touches is a valid touch.

Abstract: This application is directed to detecting touch events on a touch sensing surface coupled to a capacitive sense array and one or more force sensors. The capacitive sense array includes a plurality of sense electrodes configured to provide a plurality of capacitive sense signals. The force electrodes are configured to provide one or more force signals. In accordance with the capacitive sense signals, one or more candidate touches are detected on the touch sensing surface, and the detected candidate touches include a first candidate touch. When it is determined that force associated with the one or more force signals is associated with a grip on an edge area of the touch sensing surface, the first candidate touch is associated with the grip on the edge area of the touch sensing surface, and is designated as an invalid touch.