Abstract: A phase comparator circuit which can compare the phase of a target clock signal with the phase of a reference clock signal with a short comparison cycle. An auxiliary waveform representative of the incremental phase of each of the reference and target clock signals may be generated, and samples on the auxiliary waveforms may be compared to determine the relative phase. The result of the comparison can be used to adjust of the phase of the target clock signal. As several samples can be taken on the auxiliary waveforms, the present invention enables frequent phase comparisons. The frequent comparisons may enable the target clock signal to be synchronized quickly with the reference clock signal. The invention has particular application in display units using phase lock loops (PLLs).

Abstract: A digital display unit which accurately determines a graphics source mode using which an analog display signal has been generated. Accurate determination of the source mode enables images encoded in the received display signal to be reproduced properly on a digital display screen. Some of the display signal parameters are measured by examining the display signal. The measured parameters are compared with corresponding stored parameters for each stored mode. A match of parameters is deemed to exist if the compared values are within an associated tolerance level. A source mode matching with all matching parameter is selected to process a display signal. The tolerance level is adaptively varied to select a suitable source mode.

Abstract: A digital display unit including an analog to digital converter (ADC). When the optimal sampling frequency for sampling an analog display signal is greater than the maximum sampling frequency of the ADC, the analog display signal is sampled using 2:1' interleaved sampling. A smaller image represented by the sampled values is then upscaled prior to being displayed. Such upscaling compensates for the decreased number of samples that would be generated by sampling at lower sampling frequency during 2:1 interleaved sampling.

Abstract: A digital display unit for enabling a user to conveniently select a desired monitor mode to process a display signal. A monitor mode is generally selected by measuring some display signal parameters. If multiple source modes share the same display signal values, all the corresponding monitor modes are stored associated with these common display signal parameter values. The user is provided a convenient interface (such as pushing a button or using a menu provided with an on-screen-display) to cause the display monitor to change the monitor mode. The next monitor mode is again among those associated with the measured display signal parameter values. Accordingly, all the monitor modes associated with the measured display signal parameters can be tried using the interface until a satisfactory display is obtained on the display unit.

Abstract: An upscaler for upscaling a source image to generate a destination image without requiring large buffers. The aspect ratio (ratio of the length of the source image to that of the width) of the source image need not equal the aspect ratio of the destination image. The source image pixel data is received at a first clock rate and the destination image is generated at a second clock rate. The second clock rate is computed such that the frame rate at which the source image is received is the same as the frame rate at which the upscaled image is generated. Because of such a clock rate, the upscaler may be implemented using only a line buffer.

Abstract: A computer system in which the signal parameters of an analog display signal received by a display unit can be determined automatically. A test data having a predetermined format is sent to a display unit. The test data is encoded to enable display unit to measure display signal parameters such as the timing signals (e.g., start position of each horizontal line) accurately. The test data also includes black and white points, which enable the display unit to measure the voltage levels used to represent black and white signals. Display unit can accordingly adjust the manner in which individual points on a display screen are actuated so that the full scale of brightness levels on individual points can be utilized. CRC-based techniques are used to indicate to the display unit the presence of the test data as the same communication path is used to send test data and display data.

Abstract: A display unit which can determine the frequency (original frequency) used by a graphics source for generating an analog signal. A sequence of test patterns are generated according to a predetermined convention. The sequence of test patterns are encoded in an analog display signal in a graphics source and transmitted to a digital display unit. The digital display unit samples the analog display signal to generate a sequence of sampled values. The digital display unit determines whether the sampled values equal one of the sequence of test patterns based on the predetermined convention. The digital display unit varies (changes) the sampling frequency until the sampled values equal one of the sequence of test patterns. The sampling frequency equals the original frequency when the sampled values equal the sequence of test patterns. In one embodiment, zeros and ones are used in alternate positions of each horizontal line.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Abstract: An upscaler for upscaling a source image to generate a destination image without having to maintain the aspect ratio (ratio of the length of the source image to that of the width) of the source image. The source image pixel data is received at a first clock rate and the destination image is generated at a second clock rate. The second clock rate is computed such that the frame rate at which the source image is received is the same as the frame rate at which the upscaled image is generated. Because of such a clock rate, the upscaler may be implemented only a line buffer for upscaling a source image. Prior systems may require large memories such as frame buffers for achieving similar functionality.