Patents Assigned to Paralogic, Inc.
  • Patent number: 5471622
    Abstract: A system and method for parallel execution of logic programs on a computer network comprising two or more local-memory processors includes a logic program interpreter resident on all processors in the system. The interpreter commences execution of a logic program on one processor and, based on the results of its initial execution, generates lists of parallel-executable tasks and distributes them to other processors in the network to which it is coupled. Each processor which receives parallel tasks likewise commences execution, identification of parallel sub-tasks, and further distribution. When there are no parallel tasks at a processor or other processors available for further distributions, the task is executed sequentially and all execution results are returned to the processor which distributed the tasks executed.
    Type: Grant
    Filed: April 20, 1995
    Date of Patent: November 28, 1995
    Assignee: Paralogic, Inc.
    Inventor: Douglas J. Eadline