Abstract: A queue is disclosed (i) that provides for single-channel and multi-channel operation and that can change between single-channel and multi-channel operation during operation hitlessly, (ii) in which the number of channels and each channel's size can be changed during operation hitlessly, and (iii) is compact. To accomplish this, the illustrative embodiment comprises a group of doubly-linked lists, one for each channel's storage. One set of links indicates the node where the next datum is to be written and the other set of links indicates the node where the next datum is to be read. By bifurcating each channel's queue into a set of write links and read links, the illustrative embodiment can resize a channel during operation hitlessly.

Abstract: A method of simplifying the layout of a printed circuit board is disclosed that enables an integrated circuit to modify—after the integrated circuit is manufactured—which pads transport which signals. An integrated circuit in accordance with the illustrative embodiment comprises a two-dimensional array of pads. At the time that the integrated circuit is designed, some or all of the pads are assigned to one or more “transposition groups.” One or more pads are included in a transposition group when, for example, it might be necessary or advantageous to transpose the signals carried by those pads after the integrated circuit has been manufactured. One or more of these transpositions can, for example, greatly simplify the layout of a printed circuit board.

Abstract: A serializer and deserializer are disclosed that provide an efficient scheme for both forward error correction and symbol alignment and frame alignment by the deserializer. In particular, the illustrative embodiment provides an efficient method for generating row and column parity bits for an S by K-bit matrix that can, in some cases, require fewer that S+K parity bits. This is particularly useful for when a single word is broken up and its pieces are sent via different serial communications channels and the deserializer needs to be capable of properly reassembling the fragments into the word.

Abstract: A method for serializing bits without introducing glitches (i.e., spurious signals) into the serialized data stream is disclosed. Furthermore, the embodiments of the present invention do not require a timing signal (e.g., a clock signal, etc.) at the frequency of the serialized data stream. On the contrary, the illustrative embodiment of the present invention requires timing signals with a frequency equal to the rate at which words are loaded into the serializer. The illustrative embodiment comprises: a first unanimity gate for generating a first binary waveform based on a first coincidence function of a second binary waveform and a third binary waveform; a second umanimity gate for generating a fourth binary waveform based on a second coincidence function of the first binary waveform and a fifth binary waveform; and a first temporal delay device for receiving the fourth binary waveform and for generating the third binary waveform based on the fourth binary waveform.

Abstract: A deserializer is disclosed that incorporates a detection and feedback mechanism for ensuring that the deserializer samples a serialized stream of bits at advantageous times. Furthermore, a deserializer is disclosed that can operate at a frequency that is below the bit rate of the serialized stream of bits. The illustrative embodiment comprises: a first bi-stable storage device for receiving a first binary waveform and a first clock signal and for generating a second binary waveform based on the first binary waveform and on the first clock signal; a second bi-stable storage device for receiving the first binary waveform and a second clock signal and for generating a third binary waveform based on the first binary waveform and on the second clock signal; and unanimity logic for generating a fourth binary waveform based on a coincidence function of the second binary waveform and the third binary waveform.