Patents Assigned to Parelec, Inc.
  • Patent number: 7211205
    Abstract: Conductive ink compositions which can be cured to highly conductive metal traces by means of “chemical welding” include adhesion promoting additives for providing improved adhesion of the compositions to various substrates.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: May 1, 2007
    Assignee: Parelec, Inc.
    Inventors: Brian F. Conaghan, Gregory A. Jablonski, Paul H. Kydd, Isabel Mendoza, David L. Richard
  • Patent number: 7141185
    Abstract: Conductive ink compositions which can be cured to highly conductive metal traces by means of “chemical welding” include additives which reduce the curing temperatures for use with low-temperature substrates. Conductive ink compositions can be deposited on a substrate coated with a cure temperature reducing agent to reduce the curing temperatures.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 28, 2006
    Assignee: Parelec, Inc.
    Inventors: Brian F. Conaghan, Paul H. Kydd, David L. Richard
  • Patent number: 7115218
    Abstract: A composition of matter having a metal powder or powders of specified characteristics in a Reactive Organic Medium (ROM). These compositions can be applied by any convenient printing process to produce patterns of electrical conductors on temperature-sensitive electronic substrates. The pattern can be thermally cured in seconds to form pure metal conductors at a temperature low enough to avoid damaging the substrate.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: October 3, 2006
    Assignee: Parelec, Inc.
    Inventors: Paul H. Kydd, Gregory A. Jablonski, David L. Richard
  • Patent number: 7014727
    Abstract: A method of forming high resolution electronic circuits (10) on a substrate (12) is provided. The method includes the steps of laminating a dielectric layer (14) on a substrate (12), laser drilling channels (16 and 18) in the dielectric film (14) and the substrate (12), and filling channels (16 and 18) with a filler material (20). Further, a release layer (22) is applied to dielectric film layer (14) and filler material (20), the release layer (22) having an adhesive thereon. Release layer (22) is peeled or otherwise removed from substrate (12), leaving filler material (20) formed and shaped on substrate (12), thus producing a high resolution electronic circuit on substrate (12).
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: March 21, 2006
    Assignees: Potomac Photonics, Inc., Parelec, Inc.
    Inventors: Christopher Wargo, Paul Kydd, Scott Mathews, Susan Gordon, legal representative, Chengping Zhang, Todd A. Kegresse, Michael Duignan, deceased
  • Patent number: 6824603
    Abstract: A composition of matter comprising a mixture of an oxide powder or powders and a Reactive Organic Medium (ROM) which can be used to create electronic components on a suitable. The materials are applied to conventional polymer-based circuit substrates by any convenient printing process and thermally cured to well-consolidated oxide components at a temperature, which the substrate can withstand. Mixtures for various components, including resistors, capacitor dielectrics and magnetic cores and processes to apply them are disclosed.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: November 30, 2004
    Assignee: Parelec, Inc.
    Inventor: Paul H. Kydd
  • Patent number: 6379745
    Abstract: A composition of matter having a metal powder or powders of specified characteristics in a Reactive Organic Medium (TOM). These compositions can be applied by any convenient printing process to produce patterns of electrical conductors on temperature-sensitive electronic substrates. The patterns can be thermally cured in seconds to form pure metal conductors at a temperature low enough to avoid damaging the substrate.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: April 30, 2002
    Assignee: Parelec, Inc.
    Inventors: Paul H. Kydd, Gregory A. Jablonski, David L. Richard
  • Patent number: 6274412
    Abstract: A process sequence is disclosed for fabricating arrays of Thin Film Transistors by printing metallic conductors for the gate and data lines and possibly the Indium Tin Oxide Pixel electrode as well. The process eliminates conventional step-and-repeat photolithographic patterning, and provides high conductivity metallization for large arrays. These arrays may be used in displays, detectors and scanners.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: August 14, 2001
    Assignee: Parelec, Inc.
    Inventors: Paul H. Kydd, Sigurd Wagner, Helena Gleskova
  • Patent number: 6143356
    Abstract: PARMOD.TM. materials comprised of a metal powder or metal powder mixture of specified characteristics and a Reactive Organic Medium, are easily printed or deposited on electronic components, such as a Printed Wiring Board substrate, and cured at low temperatures to form a highly conductive, well bonded, well consolidated pure metal component. The adhesion of PARMOD.TM. conductors on an electronic component is enhanced by printing the PARMOD.TM. on a polyimide coating which has been applied to the electronic component.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: November 7, 2000
    Assignee: Parelec, Inc.
    Inventor: Gregory A. Jablonski
  • Patent number: 6036889
    Abstract: The present invention relates to a thick film formed of a mixture of metal powders and metallo-organic decomposition (MOD) compounds in an organic liquid vehicle and a process for advantageously applying them to a substrate by silk screening or other printing technology. The mixtures preferably contain metal flake with a ratio of the maximum dimension to the minimum dimension of between 5 and 50. The vehicle may include a colloidal metal powder with a diameter of about 10 to about 40 nanometers. The concentration of the colloidal metal in the suspension can range from about 10 to about 50% by weight. The MOD compound begins to decompose at a temperature of approximately about 200.degree. C. to promote consolidation of the metal constituents and bonding to the substrate which is complete at temperatures less than 450.degree. C. in a time less than six minutes.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: March 14, 2000
    Assignee: Parelec, Inc.
    Inventor: Paul H. Kydd