Abstract: In some embodiments of the present invention, frequently occurring inverse linear transform results are calculated and stored in look-up-tables. In real time, incoming blocks of linear transform coefficients are divided into two or more groups. A numerical code is determined for each group and checked against a look-up-table for that group to see whether it corresponds to a pre-calculated inverse linear transform result.

Abstract: In some embodiments of the present invention, quantized frequency coefficients of a matrix of spatial data are obtained. Blocks of frequency coefficients that will be zero-valued after quantization are identified. Only frequency coefficients belonging to other blocks are calculated explicitly using the spatial-to-frequency transform.

Abstract: The present invention is embodied in a data compression encoder for use with the discrete cosine transform compression process. The invention enhances compression using the discrete cosine transform by utilizing a prediction engine that breaks the data received into predicted and unpredicted portions. The predicted portions are excluded from the discrete cosine transform reducing the time-required to compress a file. The prediction engine relies, in part, upon look-up tables that are used to determine the predicted blocks. A table build engine and database compiler are used to create the look-up tables.

Abstract: An apparatus which generates even addressed words and odd addressed words in a memory. The apparatus consists of a port adapted for receiving an address, one or more even units in operative communication with the port and one or more odd units in operative communication with the port. The even units output an even address and the odd units output and odd address. If the input address is even the even address is equal to the input address and if the input address is odd the even address is spaced from the input address by N addresses, where N is an odd integer. If the input address is odd, the odd address is equal to the input address and if the input address is even, the odd address is spaced from the input address by N addresses.

Abstract: There is disclosed a state machine made up of a delay slot path and a no operation path, both made up of nodes with arcs connecting between them. There are arcs between the nodes of the delay slot path and the nodes of the no operation path. The number of nodes in the no operation path is equivalent to the number of available delay slots. The path taken for a specific instruction along the delay slot path, the no operation path and the arcs depends on the number of delay slots which the specific instruction utilizes. There is also disclosed a method for executing non-sequential instructions as performed by the state machine of the present invention.