Patents Assigned to Patrenella Capital Ltd., LLC
  • Ferroelectric memory with sub bit-lines connected to each other and to fixed potentials
    Patent number: 8077494
    Abstract: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: December 13, 2011
    Assignee: Patrenella Capital Ltd., LLC
    Inventor: Hideaki Miyamoto
  • Memory
    Patent number: 7933148
    Abstract: A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: April 26, 2011
    Assignee: Patrenella Capital Ltd., LLC
    Inventors: Yoshiki Murayama, Kouichi Yamada
  • Memory device configured to refresh memory cells in a power-down state
    Patent number: 7933161
    Abstract: A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained. This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell. The refresh portion reads data from and rewrites data in the memory cell in a power-down state.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: April 26, 2011
    Assignee: Patrenella Capital Ltd., LLC
    Inventors: Hideaki Miyamoto, Shigeharu Matsushita
  • MEMORY AND CONTROL UNIT
    Publication number: 20090231929
    Abstract: A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data.
    Type: Application
    Filed: March 2, 2009
    Publication date: September 17, 2009
    Applicant: Patrenella Capital Ltd., LLC
    Inventor: Hideaki Miyamoto
  • FERROELECTRIC MEMORY WITH SUB BIT-LINES CONNECTED TO EACH OTHER AND TO FIXED POTENTIALS
    Publication number: 20090231904
    Abstract: A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation.
    Type: Application
    Filed: May 22, 2009
    Publication date: September 17, 2009
    Applicant: Patrenella Capital Ltd., LLC
    Inventor: Hideaki Miyamoto