Patents Assigned to Pattern Processing Technologies, Inc.
  • Patent number: 4742555
    Abstract: A controller for operating an illumination source to illuminate selected objects to provide an image to an image transducer so that the illumination occurs at, or approximately at, the moment of time that the image of the object is desired to be acquired. An image signal manipulator receives signals corresponding to the image from the transducer.
    Type: Grant
    Filed: September 30, 1986
    Date of Patent: May 3, 1988
    Assignee: Pattern Processing Technologies, Inc.
    Inventor: Steven W. Tonkin
  • Patent number: 4551850
    Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides an address stream containing a plurality of interleaved sequences of addresses to the image buffer and to a read/write response memory. The next address of each sequence provided by the address sequencer is based upon the current address of that sequence and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address in a sequence, that address sequence is in a repetitive address loop as long as the image stored in the image buffer remains constant. During a training mode, a pattern to be recognized is supplied to the image buffer and a training code representing a desired response is written into the response memory at selected locations that correspond to addresses in the address loop being generated.
    Type: Grant
    Filed: February 7, 1983
    Date of Patent: November 5, 1985
    Assignee: Pattern Processing Technologies, Inc.
    Inventors: Larry J. Werth, Larry G. Paulson
  • Patent number: 4550431
    Abstract: An address sequencer produces an address stream which includes a plurality of interleaved sequences of addresses. Each sequence is a function of input data which is received when an input pattern is sampled by that sequence, so that a repetitive address loop is generated which characterizes the pattern. The address sequencer includes a shift register with a programmable feedback circuit which provides a feedback bit to the first stage of the shift register based upon bits from selected stages of the shift register. During each operating cycle of the address sequencer, a counter provides a sequence identification number which identifies a particular sequence. A stored address selected by the sequence identification number is provided as the present address for that sequence (and the output of the address sequencer). In addition, the shift register is loaded with a multibit word derived from that stored address.
    Type: Grant
    Filed: February 7, 1983
    Date of Patent: October 29, 1985
    Assignee: Pattern Processing Technologies, Inc.
    Inventors: Larry J. Werth, Larry G. Paulson
  • Patent number: 4541115
    Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides a sequence of addresses (or "address stream") to the image buffer and to a response memory. The next address provided by the address sequencer is based upon the current address and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address, the address stream is in a repetitive address loop as long as the image stored in the image buffer remains constant. The address loop continues to be generated, since the address sequencer always produces the same next address based upon the same current address and the same sample value stored at that current address.
    Type: Grant
    Filed: February 8, 1983
    Date of Patent: September 10, 1985
    Assignee: Pattern Processing Technologies, Inc.
    Inventor: Larry J. Werth
  • Patent number: 4504970
    Abstract: A pattern processing system associates image input patterns with desired response codes. The image input is stored in an image buffer as an addressable array of sample values. An address sequencer provides an address stream containing a plurality of interleaved sequences of addresses to the image buffer and to a read/write response memory. The next address of each sequence provided by the address sequencer is based upon the current address of that sequence and the state of the sample value stored in the image buffer at the location corresponding to the current address. Once the address sequencer repeats an address in a sequence, that address sequence is in a repetitive address loop as long as the image stored in the image buffer remains constant. The address loop continues to be generated, since the address sequencer always produces the same next address for that sequence based upon the same current address and the same sample value stored at that current address.
    Type: Grant
    Filed: February 7, 1983
    Date of Patent: March 12, 1985
    Assignee: Pattern Processing Technologies, Inc.
    Inventors: Larry J. Werth, Larry G. Paulson