Abstract: Disclosed is a three-dimensional memory having a structure including separate write wires and read wires. According to an embodiment, the three-dimensional memory may comprise: gate electrodes that are formed on a substrate to extend in the horizontal direction and are stacked and spaced apart from each other in the vertical direction; vertical channel structures that pass through the gate electrodes and extend in the vertical direction, wherein each of the vertical channel structures includes a data storage pattern, a vertical channel pattern, and a back gate; write wires for a write operation of the three-dimensional memory, each of which is arranged on top of each of the vertical channel structures and connected to the vertical channel patterns; and read wires for a read operation of the three-dimensional memory, each of which is arranged below each of the vertical channel structures and connected to the back gates.
Type:
Application
Filed:
October 24, 2023
Publication date:
July 16, 2026
Applicants:
IUCF-HYU (Industry-University Cooperation Foundation Hanyang University), PeDiSem Co., Ltd.
Abstract: Disclosed is a three-dimensional flash memory including a back gate, which includes word lines extended and formed in a horizontal direction on a substrate so as to be sequentially stacked, and strings penetrating the word lines and extended and formed in one direction on the substrate. Each of the strings includes a channel layer extended and formed in the one direction, and a charge storage layer extended and formed in the one direction to surround the channel layer, the channel layer and the charge storage layer constitute memory cells corresponding to the word lines, and the channel layer includes a back gate extended and formed in the one direction, with at least a portion of the back gate surrounded by the channel layer, and an insulating layer extended and formed in one direction between the back gate and the channel layer.
Type:
Grant
Filed:
June 22, 2021
Date of Patent:
June 27, 2023
Assignees:
IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY), PeDiSem Co., Ltd.
Abstract: Disclosed is a three-dimensional flash memory including a back gate, which includes word lines extended and formed in a horizontal direction on a substrate so as to be sequentially stacked, and strings penetrating the word lines and extended and formed in one direction on the substrate. Each of the strings includes a channel layer extended and formed in the one direction, and a charge storage layer extended and formed in the one direction to surround the channel layer, the channel layer and the charge storage layer constitute memory cells corresponding to the word lines, and the channel layer includes a back gate extended and formed in the one direction, with at least a portion of the back gate surrounded by the channel layer, and an insulating layer extended and formed in one direction between the back gate and the channel layer.
Type:
Application
Filed:
June 22, 2021
Publication date:
December 23, 2021
Applicants:
IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY, PeDiSem Co., Ltd.