Abstract: A method for identifying a table in a digital file includes extracting lines from a layout of the digital file, wherein the lines comprise horizontal lines and vertical lines. The method also includes identifying intersected line groups, wherein each intersected line group comprises a horizontal line of the extracted horizontal lines and a vertical line of the extracted vertical lines, the horizontal line and the vertical line intersecting with each other. The method further includes determining whether the number of intersected line groups is larger than a first threshold. If yes, the method further includes identifying an area in which the intersected line groups are located as a table area. If no, the method further includes performing vertical projection on characters in the area, and identifying the area as a table area based on results of the vertical projection.

Abstract: Various embodiments of exhaust valves are described. In an example, an exhaust valve assembly includes a valve body having a cylinder, a piston disposed within the cylinder, and a sealing material disposed within a trough at the bottom of the cylinder. The selection of the sealing material may be based on an operational temperature that is above a melting point of the sealing material.

Abstract: The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).

Abstract: The disclosure relates to controlling and manipulating an image of an object on a display device based on tracked eye movements of an observer. When the object is displayed according to an initial view, the observer's eye movement is tracked and processed in order to determine the focus of the observer's attention or gaze on the image. Thereafter, the displayed image is modified to provide a better view of the part of the object in which the observer is most interested. This is accomplished by modifying at least one of the spatial positioning of the object within the viewing area, the angle of view of the object, and the viewing direction of the object.

Abstract: A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.

Abstract: The invention provides a method of testing reliability of a semiconductor device, wherein the semiconductor device has negative bias temperature instability NBTI.

Abstract: The present invention relates to an image compression and decompression method, in particular in the areas of computer image processing and data compression. The currently, the process speed for which JPEG (Joint Photographic Experts Group, a compression standard) is applied, it's not all too satisfactory. One aspect of the present invention is simplify compression process based on particular features of an image, thus achieve the aim of accelerate the processing speed. Apply the process described in the present invention, the processing speed for JPEG compression/decompression would rise, without suffers quality reduction compare to current JPEG compression/decompression method.

Abstract: The invention discloses a recombinant gene which enhances the ability of fish to tolerate low dissolved oxygen (DO) stress and the use thereof. Carp ?-actin gene promoter is used as a promoter and Vitreoscilla hemoglobin gene is used as a target gene, so as to construct the recombinant Vitreoscilla hemoglobin gene driven by carp ?-actin promoter. The modeling organism zebrafish is used as the research object, and the recombinant gene is microinjected into zygotes of zebrafish. After PCR screening and 156 h low DO stress test, transgenic fish are obtained with a survival rate of 92%, which is significantly different from the survival rate of 65% of the control fish group. The vhb transgenic zebrafish obtain hypoxia tolerance. When the recombinant gene is applied to the economically farmed species, i.e., blunt snout bream (Megalobrama amblycephala) and common carp (Cyprinus carpio L.), it enhances their hypoxia tolerance as well.

Abstract: The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion impla

Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.

Abstract: The present invention discloses a method and a device for color correction for solving a problem of low color correction processing speed for images input into a computer in the prior art. A main technical solution includes: an input image is divided into no less than one image blocks; various color component values of all pixels in each image block are compared with each other, an image block with the same color component values of all pixels being regarded as a simple block, and an image block with different color component values being regarded as a complex block; and a process of color correction is performed on one pixel of the simple block, then the color correction processing result is copied to other pixels of the simple block.

Abstract: Apparatus and methods disclosed herein provide for a set of reference images obtained from a camera and a reference image obtained from a viewpoint to capture an entire concave region of an object; a silhouette processing module for obtaining a silhouette image of the concave region of the object; and a virtual-image synthesis module connected to the silhouette processing module for synthesizing a virtual inside-out image of the concave region from the computed silhouette images and for generating a visual hull of the object having the concave region.

Abstract: The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process.

Abstract: An all-fiber interferometric fiber optic gyroscope having a minimum reciprocal configuration is described. The gyroscope comprises a light source, a light detector, a light source coupler, a fiber optic loop coupler, and a polarization maintaining fiber optic loop. A first port of the light source coupler is coupled, with polarization axis alignment, to an output end of the light source, and a second port of the light source coupler on the same side as the first port is coupled to the light detector. A third port on the other side of the light source coupler is coupled, with polarization axis alignment, to the fiber optic loop coupler, and the fiber optic loop coupler is coupled, with polarization axis alignment, to the polarization maintaining fiber optic loop. The light source splits the input light and polarizes the optical signal propagated along a transmission arm alone, where the first and third ports are on the same transmission arm.

Abstract: The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers.

Abstract: The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.

Abstract: The disclosure relates generally to receiving original image data, decomposing the original image data into layers, compressing a dynamic range of each of layers, and integrating compressed layers to form a final image.

Abstract: The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same.

Abstract: Embodiments of the present disclosure relate to the field of printed circuit boards and particularly to a multi-layer printed circuit board. The multi-layer printed circuit board includes at least two inner-layer circuit boards, each of which has a non-circuit pattern area including a welding area. Each welding area has at least one welding hole. Further, at least one prepreg is used to fill between two adjacent inner-layer circuit boards and is melted to fill into the welding hole in a welding process. In the multi-layer printed circuit board according to the embodiments of the disclosure, a welding area is arranged in a non-circuit pattern area, and one or more welding holes are arranged in the welding area so that a prepreg between two inner-layer circuit boards can be melted filling into the welding hole(s) in a welding process, thus enhancing effectively an adhesive force binding the inner-layer circuit boards.

Abstract: A digital right management method, including: generating, by a first user equipment having access right to shared digital contents, a common public key based on one or more public keys of one or more second user equipments intended to share the digital contents, respectively; encrypting, by the first user equipment, a key of the digital contents with the common public key to generate a ciphertext of the key of the digital contents; generating, by the first user equipment, from the ciphertext a new authorization certificate corresponding to the digital contents; and transmitting, by the first user equipment, the new authorization certificate and the digital contents to the second user equipments to instruct the second user equipments to share the digital contents in accordance with the new authorization certificate.