Abstract: A high-speed bus system which combines at least one parallel bus and at least one serial bus for simultaneous parallel and serial data transfer with serial data transfer taking place after connection setup at the same time as normal transfer of data and/or programs takes place on the parallel bus. Connection setup for both parallel and serial data transfer uses the logic circuit of the parallel bus. The particular adaptability of the high speed bus system is also achieved by using a high speed serial/parallel and parallel/serial converter which is connected between a parallel bus and a serial bus. This high speed serial/parallel and parallel/serial converter contains two functional units, one functional unit contains a no-delay start/stop oscillator and the other functional unit contains an internal control logic circuit which generates a busy signal when the serial bus is occupied.