Abstract: A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

Abstract: A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control code that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. The PLL may be implemented with dedicated or off-the-shelf circuitry, in an FPGA, or with a programmable processor. A tangible non-transitory memory may hold an associated software instructions for fractional-N phase locking.

Abstract: A phase-locked loop (PLL) has at least two parallel loops. The loops share an oscillator, a counter connected with the oscillator, a multiplexer, and a loop filter. Each loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The loop forwards the integer difference between the sampled phase and the predicted phase to the multiplexer, which selects one of the loops and provides the difference to the loop filter. Loops that are not selected use a monitor-and-adjust function to keep the difference in track with the difference of a selected loop. Loops may provide a loop sleep function and the PLL may also provide an oscillator sleep function.

Abstract: A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

Abstract: A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control code that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. The PLL may be implemented with dedicated or off-the-shelf circuitry, in an FPGA, or with a programmable processor. A tangible non-transitory memory may hold an associated software instructions for fractional-N phase locking.

Abstract: A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control signal that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. A first sleep mode control signal blocks a reference clock and feedback of the oscillator clock to the counter. It may also freeze loop filter parameters and block the output clock. A second sleep mode control signal may stop the oscillator.

Abstract: A phase-locked loop (PLL) has at least two parallel loops. The loops share an oscillator, a counter connected with the oscillator, a multiplexer, and a loop filter. Each loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The loop forwards the integer difference between the sampled phase and the predicted phase to the multiplexer, which selects one of the loops and provides the difference to the loop filter. Loops that are not selected use a monitor-and-adjust function to keep the difference in track with the difference of a selected loop. Loops may provide a loop sleep function and the PLL may also provide an oscillator sleep function.

Abstract: A phase-locked loop (PLL) has a primary loop (with a reference clock) and a secondary loop (with a stable reference clock). The secondary loop may include a fractional-N PLL, and may include a secondary loop filter, oscillator, output clock counter, and phase predictor using a rational secondary frequency control word (FCW). The primary loop has a register sampling the oscillator phase from the counter, and a phase predictor which uses a primary fractional-N FCW to calculate a predicted phase as an integer number. The primary loop forwards the integer difference between the sampled phase and the predicted phase to a primary loop filter, which outputs the secondary FCW. The primary loop filter has a much lower bandwidth than the secondary loop filter. The PLL may have multiple primary loops, with a hitless switching function. A primary loop may have sleep mode. The PLL may also provide an oscillator sleep function.

Abstract: A block of logic gates has MOS transistors whose body terminals are connected with a body voltage rail and whose source terminals are connected with a logic reference voltage rail. The logic reference voltage rail is connected to the body voltage rail via a resistor. The resistor creates a negative feedback loop for leakage currents that stabilizes a reverse body bias voltage and reduces the influence of temperature, voltage, and process variations. The block may be NMOS, PMOS, or CMOS. In the case of CMOS, there are two body voltage rails, powered by a voltage source, two logic reference voltage rails, and two resistors. The reverse body bias voltages over the two resistors may be stabilized by decoupling capacitors. The two resistors may be trimmable. The resistors may be calibrated such that leakage currents are at a minimum value and the logic gates can switch just fast enough.

Abstract: A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.

Abstract: A fabric for delaying digital signals in continuous time has an array of node filters. Inputs of filters in the first column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form an output signal of the filter. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other rows of the array. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements. A delay line is constructed by combining a phase generator and a fabric, where the phase generator splits a digital input signal in multiple incrementally delayed versions for the fabric inputs.

Abstract: Devices, systems, and methods determine the health of oral objects by providing objective measurements using a detachable probe body. The detachable probe body may isolate reusable system components (including an electromagnetic signal detection, signal transmission, energy generation, and or energy transmitting components) from the oral cavity, optionally by encasing at least a portion of one or more of these components in a sheath or the like. A window of the probe body maintains sterile isolation and transmits electromagnetic energy to and/or signals from the oral object. Accuracy can be enhanced by a clamp or other structure for engaging a surface of the oral object so as to maintain a fixed alignment between the signal receiver and the oral object.