Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: Differential buffers are described that combine aspects of voltage-mode buffers with current injection to achieve the tunability associated with current-mode buffers as well as the low current and low power associated with voltage-mode buffers.

Abstract: A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Abstract: An in-situ unplug detector circuit detects when a cable is disconnected or unplugged. Detection does not have to wait for normal signaling to pause, such at the end of a frame or timeout. Instead, detection occurs during normal signaling. When the cable is disconnected, the transmitter no longer drives the load at the far end of the cable, and thus can drive the near end to a higher high voltage and to a lower low voltage. The increased voltage swing is detected by a detector at the near end that amplifies the transmitter output to the cable. A fast detector has a higher bandwidth and faster response time than a slow detector, and generates a fast detect signal that crosses over a slow detect signal. When the cable is disconnected, the fast detect signal again crosses over the slow detect signal, and decision logic activates an unplug signal.

Abstract: A re-driver circuit has pre-driver, intermediate, and output stages. Pre-emphasis on the output is generated by the intermediate stage and injected into an output stage. The intermediate stage is a frequency-tuned amplifier that has an inductive-capacitive L-C tank circuit that is tuned to a desired frequency of the output. The intermediate stage does not directly drive the output stage. Instead, an on-chip coupling transformer couples the L-C tank circuit to the output stage. The coupling transformer has a first inductor that is part of the L-C tank circuit in the intermediate stage, and a second inductor that is part of the output stage. Mutual inductance between the first inductor and the second inductor inductively couple a pre-emphasis voltage onto the output. The magnitude of the pre-emphasis can be changed by adjusting current in the intermediate stage.

Abstract: A re-driver circuit has pre-driver, intermediate, and output stages. Pre-emphasis on the output is generated by the intermediate stage and injected into an output stage. The intermediate stage is a frequency-tuned amplifier that has an inductive-capacitive L-C tank circuit that is tuned to a desired frequency of the output. The intermediate stage does not directly drive the output stage. Instead, an on-chip coupling transformer couples the L-C tank circuit to the output stage. The coupling transformer has a first inductor that is part of the L-C tank circuit in the intermediate stage, and a second inductor that is part of the output stage. Mutual inductance between the first inductor and the second inductor inductively couple a pre-emphasis voltage onto the output. The magnitude of the pre-emphasis can be changed by adjusting current in the intermediate stage.

Abstract: A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Abstract: A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Abstract: Distortions of both amplitude and phase along a transmission line are compensated for by a trace canceller inserted between a transmitter and a receiver. The trace canceller has an equalizer that compensates for a trace length between the transmitter and the trace canceller. A variable gain amplifier between the equalizer and an output buffer has its gain controlled by an automatic gain control circuit that compares low-frequency swings of the input and output of the trace canceller. The gain of the variable gain amplifier is reduced to prevent the output buffer from saturating and clipping peak voltages on its output. Thus both the variable gain amplifier and the output buffer remain in the linear region. Training pulses from the transmitter are passed through the trace canceller without clipping of peak voltages, allowing the transmitter and receiver to adjust transmission parameters to best match the transmission line.

Abstract: A dual-output triple-Vdd charge pump as two pumped outputs that are both pumped to three times the power-supply voltage, 3×Vdd. This pumped output voltage is reduced by two p-channel inner diode drops, to 3×Vdd?2×|Vtp|. A pair of cross-coupled n-channel transistors alternately charge two inner nodes from the power supply. Inner pumping capacitors drive inner nodes between Vdd and 2×Vdd, and the cross-coupling of the gates turns off one of the cross-coupled n-channel transistors when its inner node is being driven high. A p-channel inner diode transistor connects an inner node to an outer node, causing a |Vtp| drop. The outer node is also pumped by an outer pumping capacitor that drives the outer node between 2×Vdd?|Vtp| and 3×Vdd?|Vtp|. A p-channel outer diode transistor conducts from the outer node to the pumped output node, causing another |Vtp| voltage drop. The pumped output voltage is maintained at 3×Vdd?2×|Vtp| by an output capacitor.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: Power-down mode is activated when equal voltages are detected on a pair of differential inputs. The voltage difference across the differential inputs is equalized by an equalizer and then applied to a multiplier and smoothed and filtered by a low-pass filter to produce an average signal. The average signal is compared to a reference voltage to detect when the voltage difference across the differential inputs is too small. A power-down signal is activated when the average signal is too small. The reference voltage compared can be generated by an equalizer, multiplier, and low-pass filter to match process, temperature, and supply-voltage variations in the primary signal path. The multipliers can be implemented with Gilbert cells. The equalizers can receive control signals to control attenuation of different frequency components.

Abstract: A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Abstract: A switch fabric that carries analog differential signals is constructed from 2×2 switches. Each 2×2 switch has two differential inputs that are applied to two demultiplexers. Each 2×2 switch also has two differential outputs, each driven by an equalizing mux. Each demultiplexer has two amplifiers that drive intermediate differential signals to the two equalizing muxes. Each equalizing mux has two equalizers that receive the intermediate differential signals from the two demultiplexers. A select signal enables one equalizer but disables the other to select one of the two intermediate differential inputs. A combining amplifier receives differential outputs from both equalizers and generates a final differential output. R, C values in each equalizer can be adjusted to compensate for loading variations in the intermediate differential signals which can have different physical lengths in a switch fabric.

Abstract: A swivel adapter connects plugs for different video-connector standards. A smaller Display-Port (DP) connector fits into ports on a personal computer or other device, while a larger Digital Visual Interface (DVI) connector connects to a display or other device through a standard cable. When computer DP ports are tightly spaced, the wider DVI end of the swivel adapter can be twisted to make room for other DP plugs to fit into other DP ports on the computer. A swivel mechanism is located within the adapter body between DP-connector and DVI-connector ends of the adapter body. A swivel joint between the two ends rotates as the swivel mechanism is twisted. Two circuit boards in either end are connected together through the swivel joint by flex lines or a flexible circuit board. A converter chip on one circuit board converts signals between the DP and DVI formats.

Abstract: A Pseudo-Ethernet switch has a routing table that uses Ethernet media-access controller (MAC) addresses to route Ethernet packets through a switch fabric between an input port and an output port. However, the input port and output port have Peripheral Component Interconnect Express (PCIE) interfaces that read and write PCI-Express packets to and from host-processor memories. When used in a blade system, host processor boards have PCIE physical links that connect to the PCIE ports on the Pseudo-Ethernet switch. The Pseudo-Ethernet switch does not have Ethernet MAC and Ethernet physical layers, saving considerable hardware. The switch fabric can be a cross-bar switch or can be a shared memory that stores Ethernet packet data embedded in the PCIE packets. Write and read pointers for a buffer storing an Ethernet packet in the shared memory can be passed from input to output port to perform packet switching.

Abstract: A network connection is transparently shared among two or more processors. A shared network interface controller (NIC) has two or more sets of context registers that may include Ethernet command and pointer registers. Each set of context registers is accessed by a different processor. The processors are separated from the shared NIC by an Advanced Switching (AS) network. AS packets to write the context registers are embedded in AS packets that contain turnpool information that specifies a route through the AS network. Turnpools for AS packets from the different processors are unique and used to indicate which set of context registers to access. Each turnpool-identified context is assigned a different external network (Ethernet) address. External packets received by the shared NIC from the external network are sent inside AS packets over the AS network to the correct processor by associating the packet's external network address with a turnpool-context.

Abstract: An adjustable-delay filter performs wave shaping to emulate pre-emphasis or de-emphasis of transmission-line signals. The adjustable-delay filter uses analog components and does not need a clock. The receiver does not have to recover a bit-clock from the data stream, eliminating a clock recovery circuit. An input buffer receives the input signal and drives current to a summer and to an adjustable delay. The adjustable delay inverts and delays the current and drives a delayed, inverted current to the summer. The summer combines the delayed, inverted current and the current from the input buffer to generate an output signal. The delay time of the adjustable delay can be programmed by a user and is less than the bit period. After a signal transition, the output signal initially spikes higher, then falls back to a nominal level after the delay time has expired. The initial signal spike emulates de-emphasis or pre-emphasis.

Abstract: A clock generator corrects the duty cycle of an input clock. The input clock has a poor duty cycle such as less than 50%. The input clock is applied to a phase detector of a phase-locked loop (PLL). A voltage-controlled oscillator (VCO) of the PLL drives a feedback clock that is also applied to the phase detector. An edge-triggered set-reset SR flip-flop generates a duty-cycle-corrected output clock. The SR flip-flop is set by the leading edge of the input clock, but is reset by the trailing edge of the feedback clock. The VCO generates the feedback clock with the desired duty cycle, such as 50%. The leading edge of the output clock is generated by the input clock, avoiding noise generated by the PLL, while the trailing edge of the output clock is generated by the feedback clock and has PLL noise, but corrects for the desired duty cycle.

Abstract: Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. Some lanes are directly connected from the root complex host to each slot. Each slot is driven by a different port and a different direct physical layer on the host. Other lanes are configurable and can be driven by any port and use a configurable physical layer on the host. These configurable lanes pass through an external switch or crossbar that connects the lanes from the host to one or more of the slots. The direct-connect lanes can be the first lanes to a slot while the configurable lanes are the higher-numbered lanes.