Abstract: An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Thk used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Thki may be calculated for each bit position. Thki and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

Abstract: An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Thk used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Thki may be calculated for each bit position. Thki and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

Abstract: A storage device includes 3D NAND including layers of multi-level cells. When a shutdown command is received, whether a block is partially written is evaluated. If so, dummy lines are written after the last written wordline of the block. Partially written blocks may be those having a fill percentage less than a threshold. The threshold may be a function of the PEC count of the block. If a maximum retention time is exceeded by data stored in a partially written block, dummy lines may also be written to the block.

Abstract: A PCIe architecture is disclosed incorporating a controller memory buffer (CMB). Write data is written to the CMB and is not read out for processing upon receiving a write command for the write data. The data is read out of the CMB and processed to obtain processed data upon receiving feedback from a NAND channel controller. The processed data may be written directly to the NAND channel controller or may be written to a light write buffer that is read by the NAND channel controller. The processed data may be written to a light write buffer functioning as a cut through buffer.

Abstract: Read latency for a read operation to a host implementing a PRP/SGL buffer is reduced by generating an address table representing the linked-list structure defining the PRP/SGL buffer. The address table may be generated concurrently with reading of data referenced by the read command from a NAND storage device. A block table for tracking status of LBAs referenced by IO commands may include a reference to the address table which is used to transfer LBAs to host memory as soon as the address table is complete and a block of data referenced by an LBA has been read from the NAND storage device.

Abstract: Example near-memory computing systems and methods are described. In one implementation, a system includes a host command processing system and a computational engine associated with a solid-state drive. In some situations, the computational engine includes multiple versatile processing unit slices coupled to one another. The multiple versatile processing unit slices are configured to perform different tasks in parallel with one another. The system also includes a host direct memory access module configured to access memory devices independently of a central processing unit.

Abstract: A storage device includes 3D NAND including layers of multi-level cells. Test reads are performed by reading only LSB pages and reading layers in a repeating pattern of reading two and skipping two. A test read of a block is performed when its read count reaches a threshold. The counter threshold is updated according to errors detected during the test read such that the frequency of test reads increases with increase in errors detected. Counter thresholds according to errors may be specified in a table. The table may be selected as corresponding to a range of PEC values including the current PEC count of the 3D NAND. Each table further specifies a number of errors that will result in garbage collection being performed.

Abstract: Example computational storage systems and methods are described. In one implementation, a storage drive controller includes a non-volatile memory subsystem to process multiple commands. Multiple versatile processing arrays are coupled to the non-volatile memory subsystem. The multiple versatile processing arrays can process multiple in-situ tasks. A host direct memory access module provides direct access to at least one memory device.

Abstract: The present invention extends to methods, systems, and computer program products for dynamically throttling host write data rates, for example, at SSDs. Host write data is received from a host at a host write data rate. The host write data is buffered in an SSD buffer at the host write data rate. Some host write data is transferred from the SSD buffer to NAND storage at an internal NAND data rate. A host write throttle is calculated at least based on the host data rate and the internal NAND data rate. The host write throttle defines a new (e.g., increased or decreased) host write data rate. The host write throttle is sent to the host requesting the host utilize the new host write data rate. When a new host write data rate is decreased, data transfer from SSD buffer to NAND storage can be allowed to “catch up”.

Abstract: Example storage control systems and methods are described. In one implementation, a storage drive controller includes a non-volatile memory subsystem that processes multiple commands. The storage drive controller also includes a controller memory buffer (CMB) memory management unit coupled to the non-volatile memory subsystem. The CMB memory management unit manages CMB-related tasks including caching and storage of data associated with the storage drive controller.

Abstract: A memory module includes arrays of memory devices each having a data bus coupled to the data bus of a host memory channel by means of a switching tree. The switching tree is a tree of multiplexers that are controlled to couple the data lines of a single array to the data bus. In some embodiments, a first portion of the chip enable (CE) lines of a memory module are used to enable arrays of memory devices and a second portion are used to control the switching tree. The first portion may control a switching tree coupling the first portion to the enable inputs of the arrays.

Abstract: A peripheral device implements a plurality of queue sets each including a submission queue and a completion queue. Changes to the queues are monitored and arbitration parameters are adjusted, the arbitration parameters defining how submission queues are selected for retrieval of a command. An arbitration burst for a submission queue may be increased in response to tail movement for the submission queue being larger than for another submission queue. Priorities used for weighted round robin arbitration may also be adjusted based on tail movement. Arbitration burst quantities and priorities of groups of queues may also be adjusted. Head movement of the completion queues is monitored and may be used to lower priority, enable interrupt coalescing, or pause command retrieval where head movement does not meet a threshold condition.

Abstract: A storage device implements striping logic with respect to a plurality of slices, each slice including one or more storage media, such as NAND flash dies. Data operations are distributed among the slice in an unequal manner such that the frequency of selection of a slice decreases with number of defects in the NAND dies of that slice. For example, data operations may be distributed in a round-robin fashion with some slices being skipped periodically. In some embodiments, a skip map may be used that maps host addresses (HLBA) to a particular slice and device address (DLBA) in that slice, the skip map implementing the skipping of slices. The skip map may be smaller than the size of the storage device such that each HLBA is mapped to a zone of the storage device and a slice and offset within that zone are determined according to the skip map.

Abstract: A bit flipping algorithm for an LDPC decoder evaluates a data sequence d with respect to a parity code matrix H. Where one or more checks fail, bits of d are flipped such that for some iterations, the bits are flipped with bias toward and original data sequence r. For example, for some iterations, where the number of failed checks are below a first threshold T1, bits are only permitted to flip back to the value of that bit in the original data sequence r. In such iterations, bits are permitted to flip from the value in the original data sequence r only when the number of failed checks is greater than a second threshold T2, T2>T1. Values for thresholds may be based on a number of flipped bits from a previous iteration and may be calculated using a syndrome s=Hd from a previous iteration.

Abstract: A flow controller selects a direction (encryption/decryption) for an AES core according to quality of service parameters and a number of data words in encryption and decryption data buffers. A direction ratio may be calculated as a function of the quality of service parameters and the number of data words in the encryption and decryption data buffers. The flow controller selects the direction to reduce a cost function. The cost function may be at a minimum when a ratio of words in the encryption and decryption data buffers is the same as the direction ratio. A key management unit supplies keys according to the selected direction to the AES cores. Multiple AES cores may be used.