Abstract: A charge storage cell includes a conductive substrate, a substantially vertical post comprising a first insulating material coupled to the conductive substrate and a conductive cap coupled to the vertical post. The charge storage cell also includes a top side planarizing layer comprising a second insulating material and covering the conductive cap. The conductive cap will support an electric charge injected through the top side planarizing layer by a modulated charged particle beam.

Abstract: A multi-channel timing device is described that can be completely controlled by a user's voice for hands free operation, and has a wireless communications link to a mobile device. Preferably the timing device comprises a processor, a memory, a display, a microphone, a speaker, a processor, a transceiver, and an audio chip. The memory contains instructions executable by the processor to facilitate the creation, control and reporting of multiple timing channels, for example six or more channels. The audio chip performs speech recognition, speech synthesis, and music synthesis. A rich set of event sequencing scenarios are executable by pairing the timing device with a mobile device, such as locating, retrieving and executing recipes that are preprogrammed in a suitable format in the mobile device. The mobile device can also serve as a surrogate to the user, and the pair of devices can implement an event sequencing system having local or remote control capabilities.

Abstract: A charge array wafer includes a plurality of electrical charge storage cells disposed in an array configuration. A programmable amount of charge in each of the electrical charge storage cells causes a predetermined electric field to extend from a charge storage layer, through a passivation layer and into the space above the passivation layer, and the predetermined electric field is operable to attract deposition material to the top surface of the passivation layer. The deposition material may be a gas, a liquid or a powder, having a minimum feature size ranging from tens of nanometers to around five microns. The array of electrical charge storage cells includes an uninterrupted two-dimensional array extending over greater than 100×100 electrical charge storage cells without a select gate and without a bit-line contact positioned between any of the electrical charge storage cells.