Patents Assigned to PEZY COMPUTING K.K.
  • Patent number: 10818638
    Abstract: A set of the dies and the package are provided with a plurality of dies each including at least an accelerator core or a CPU core, an external interface, memory interfaces, and a die interface for connecting to another die. At least two dies of the set of dies include a first type die and a second type die each including both the accelerator core and the CPU core, and the core number ratio between the accelerator core and the CPU core in the first type die differs from that in the second type die. The memory interfaces include an interface conforming to TCI. The memory interfaces further include an interface conforming to HBM.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 27, 2020
    Assignee: Pezy Computing K.K.
    Inventor: Motoaki Saito
  • Patent number: 10691634
    Abstract: Provided efficiently and at low cost are: a package for core number ratios appropriate for all types of computers; and dies included in the package. This package includes at least one die provided with: at least one of a first core formed of a CPU core or a latency core and a second core formed of an accelerator core or a throughput core; an external interface; memory interfaces 24 to 26; and a die interface 23 which is connected to another die. The die includes a first type die and a second type die each including both the first core and the second core and the core number ratio between the first core and the second core in the first type die differs from that in the second type die. Moreover, the memory interfaces include an interface conforming to TCI. In addition, the memory interfaces further include an interface conforming to HBM.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: June 23, 2020
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10505589
    Abstract: A signal bridge device is provided with a plurality of bridge signal transmission/reception units, a plurality of bridge signal transmission/reception terminals, and a bridge signal distribution unit. Non-contact reception signals received by the bridge signal transmission/reception units are input into the bridge signal distribution unit. Contact reception signals received by the bridge signal transmission/reception terminals are input into the bridge signal distribution unit. The bridge signal distribution unit can output the non-contact reception signals to the bridge signal transmission/reception terminals and can output the contact reception signals to the bridge signal transmission/reception units.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: December 10, 2019
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10396856
    Abstract: A semiconductor device includes a first semiconductor chip and a second semiconductor chip The first semiconductor chip includes a transmission circuit input unit, a transmission circuit unit, and a transmission unit. The second semiconductor chip includes a reception unit, a reception circuit unit, and a reception circuit output unit. The transmission unit and the reception unit can communicate with each other in a non-contact manner. A transmission circuit unit input signal having a predetermined transmission-side potential is input into the transmission circuit unit. A reception circuit unit input signal is input into the reception circuit unit via the non-contact communication between the transmission unit and the reception unit. The reception circuit unit outputs a reception circuit unit output signal having a predetermined reception-side potential. The ratio of the reception-side potential to the transmission-side potential can be changed.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 27, 2019
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10304806
    Abstract: A semiconductor device includes multiple semiconductor chips and a control unit. Each of the semiconductor chips has multiple signal processing units that can be connected with each other, multiple in-chip signal lines that are respectively connected to the signal processing units and that can be connected with each other, and a connection-state changing unit that changes the connection state between the in-chip signal lines according to an instruction from the control unit. The connection-state changing unit of each semiconductor chip changes the connection state between the in-chip signal lines according to the instruction from the control unit, so that the connection state between the signal processing units is changed.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 28, 2019
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito
  • Patent number: 10192836
    Abstract: A semiconductor device equipped with a base board, a first element, a second element, and an interposer board, wherein: the first element is positioned on the base board; a signal transmitting/receiving terminal of the first element and a plurality of base board terminals contact one another; the second element is positioned on the base board; a signal transmitting/receiving terminal of the second element and the plurality of base board terminals contact one another; the interposer board is positioned so as to extend on the first element and the second element; a first contactless signal transmitting/receiving unit of the interposer board is capable of contactlessly transmitting and receiving a signal; and a second contactless signal transmitting/receiving unit of the interposer board is capable of contactlessly transmitting and receiving a signal.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: January 29, 2019
    Assignee: PEZY COMPUTING K.K.
    Inventor: Motoaki Saito