Abstract: A video signal waveform monitor is shown, which receives an input video signal composed of video lines. A video signal digitizer samples the input video signal at video sample points to generate a sequence of video pixel data, which is written into an acquisition framestore is organized into a video pixel array so as to represent a raster of the input video signal. A level analyzer reads the video pixel data row-by-row from segments of the video pixel array and increments video level data at addresses in cache memory in response to the serially-read video pixel data. This generates a sequence of video level data, which is written into an output framestore and which represents the level of the waveform of the input video signal. The segments of the video pixel array comprise at least one and less than all of the columns in the video pixel array.

Abstract: A video signal waveform monitor is shown, which receives an input video signal composed of video lines. A video signal digitizer samples the input video signal at video sample points to generate a sequence of video pixel data, which is written into an acquisition framestore is organized into a video pixel array so as to represent a raster of the input video signal. A level analyzer reads the video pixel data row-by-row from segments of the video pixel array and increments video level data at addresses in cache memory in response to the serially-read video pixel data. This generates a sequence of video level data, which is written into an output framestore and which represents the level of the waveform of the input video signal. The segments of the video pixel array comprise at least one and less than all of the columns in the video pixel array.

Abstract: A jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, is shown. A clock recovery circuit (401) recovers a clock signal from the test signal and a synchronization circuit generates a synchronized system clock signal from said recovered clock signal. A sinusoid generator (403) generates a sinusoid signal from the synchronized system clock signal and a sampling analog to digital converter (404) samples the sinusoid signal by the recovered clock signal to provide sinusoid samples further comprising: A numerically controlled oscillator (401) is configured to produce sine values and cosine values in response to receiving an input from the system clock signal and a first multiplier (412) is configured to produce a first product of the sinusoid samples and the sine values. In addition, a second multiplier is configured to produce a second product of the sinusoid samples and the cosine values.