Abstract: An circuit arrangement and method utilize scheme registers to select among a plurality of indirect address registers from which to retrieve a stored memory address. Rather than identifying within an instruction the location of a particular indirect address register within which is stored an address to be used during processing of the instruction, the instruction specifies the location of a scheme register that identifies which of a plurality of available indirect address registers should be accessed to retrieve a stored address. Scheme registers may be used, for example, in digital signal processing applications to efficiently encode multiple independent addresses within a DSP instruction.

Abstract: A method, a circuit arrangement and an apparatus are provided for evaluating an input data signal transmitted by load modulation. A complex data signal is derived from the input data and a mean value signal of the complex data signal is thereafter derived. A complex signal without mean value is also formed from the difference between the complex data signal and the mean value signal of the complex data signal. A first and second quadratic error signals are derived and subsequently a slope signal is derived from the first and second quadratic signals. The method also comprises deriving an information signal by comparing the imaginary part signal without mean value with a decision threshold signal. The information signal indicates whether a value of the input data signal has been generated in a loaded state or an unloaded state during the load modulation.

Abstract: A method of manufacturing semiconductors is provided which avoids metal deposition in voids formed in the dielectric between interconnects. In a preferred embodiment, an etch stop recess portion is provided over the dielectric which encloses the interconnects to prevent via openings from extending into the voids during the etching of the via openings. Accordingly, metal deposition of the voids during metal deposition of the vias is avoided. As a result, the semiconductors so formed has reduced capacitance between the interconnects and improved reliability since the voids are cleared of any metal deposition.

Abstract: A set-associative cache-management method combines one-cycle reads and two-cycle pipelined writes. The one-cycle reads involve accessing data from multiple sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. The two-cycle write involves finding a match in a first cycle and performing the write in the second cycle. During the write, the first stage of the write pipeline is available to begin another write operation. Also, the first-stage of the pipeline can be used to begin a two-cycle read operation-which results in a power saving relative to the one-cycle read operation. Due to the pipeline, there is no time penalty involved in the two-cycle read performed after the pipelined write. Also, instead of a wait, a no-op can be executed in the first stage of the write pipeline while the second stage of the pipeline is fulfilling a write request.

Abstract: A method for inspecting a reticle to evaluate the degree of corner rounding of a feature of a test pattern includes placing a reticle having a photomask formed thereon under a microscope. The photomask has a pattern corresponding to features of a semiconductor chip design defined therein. In addition, the photomask further has a test pattern and a crosshair orientation mark defined therein. The test pattern has at least one test corner for evaluating a degree of corner rounding when the test pattern is defined in the photomask. The crosshair orientation mark is defined in the photomask to orient a crosshair of the microscope relative to the test pattern. Once the crosshair of the microscope is aligned with the crosshair orientation mark, the crosshair of the microscope is used to evaluate the degree of rounding of the test corner of the test pattern.

Abstract: The present invention provides an LDO that is stable for all capacitive loads. Because the LDO is stable for all capacitive loads, the ESR (equivalent series resistance) inherent in any capacitive load can no longer affect the equivalent value of the combination of the ESR and the capacitive load. Thus, the invention also effectively removes the ESR restrictions on the loads. According to the present invention, a low dropout voltage regulator is provided. The regulator comprises a switching element (e.g., a transistor) having first terminal for receiving an input signal, a second terminal for providing an output signal and a control terminal; a control circuit, operably coupled to the switching element, that is configured to control the switching element; and a compensation circuit having a first segment connected between the first and control terminals of the switching element and a second segment connected between the control and second terminals of the switching element.

Abstract: In a dual-damascene method for forming an integrated circuit with copper conductors, a fluorinated silicon oxide (SiOF) marker layer is formed between an intermetal silicon dioxide layer and an upper silicon dioxide layer. A plasma etch forms trenches (as sited for future copper conductors) in the upper silicon dioxide layer according to a pattern defined by a photoresist mask. During this trench etch, the spectral characteristics of the plasma are monitored. After the marker layer is exposed and etching of the SiOF begins, an optical spectral detector detect is an enhancement of a spectral signal associated with fluorine ions. This detection is used in determining when to terminate the trench etch. A further photolithographic step results in via apertures. The trenches are then filled with copper. The resulting structure includes marker material in areas protected by the trench etch mask. However, because the dielectric constant of fluorinated silicon oxide (k=3.3-3.

Abstract: Logic circuitry performs a matching algorithm function. A memory produces a match signal that indicates which memory cells contain data that matches input address data to the memory. A first logic AND function performs a logic AND between a current value of the match signal currently produced by the memory for the input address data with a prior value of the match signal produced by an immediately prior input address data. A buffer holds index data. A second logic AND function compares output of the first logic AND function with the index data. Output of the second logic AND function is returned to the buffer as new index data. Index logic generates an offset based on the index data stored in the buffer. A send byte function asserts a send byte signal when the match signal is zero and when the output of the second logic AND function is zero. A length counter is incremented for every cycle in which the send byte signal is not asserted.

Abstract: A cryptographic device includes a de-multiplexer, a plurality of encryption blocks, a plurality of permutation blocks, and a multiplexer. The encryption blocks encrypt data to produce encrypted data. The de-multiplexer receives data portions from a plaintext message and directs the data portions to one of the encryption blocks, based on a value within a path control session key. Each permutation block is associated with an encryption block. Each permutation block permutes encrypted data from the encryption block associated therewith. The multiplexer receives data portions from each of the plurality of permutation blocks to produce an encrypted output data stream.

Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of an immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. The single-set reads save power relative to the parallel reads, while maintaining the speed advantages of the parallel reads over serial “tag-then-data” reads.

Abstract: A method for depositing a liner dielectric on a semiconductor substrate provides for sufficient adhesion of low dielectric constant spin-on materials among metal layers in sub-micron processes. In an example embodiment, a method for adhering MSQ provides for a liner oxide on an aluminum alloy layer on a semiconductor substrate. First, the substrate is placed into a PECVD environment. A gas mixture of trimethylsilane and N2O is introduced into the PECVD environment at a trimethylsilane-to-N2O ratio of about 1:20 to 1:30. The gas mixture is reacted to deposit an oxide liner of a predetermined thickness. Adjusting the gas mixture trimethylsilane-to-N2O ratio to about 1:3 to 1:7 over the course of about 5 to 20 seconds, and sustaining the reaction thereof, deposits a methyl doped oxide.