Abstract: Signal correction in a bipolar transistor circuit having a base-emitter voltage and a non-linear output signal corresponding to a detectable characteristic is improved by correcting non-linearity in the signal at third and/or higher-orders. According to an example embodiment of the present invention, the output of the transistor is corrected as a function of the base-emitter voltage, the non-linear output signal and a generated non-linearity. The generated non-linearity is adapted to cancel the non-linearity of the non-linear output signal when added thereto. Various implementations of the present invention are applicable to a variety of applications, each of which may have selected characteristics that are accounted for by the generated non-linearity, which is selectively adapted for each particular application. In this manner, third and higher-order corrections can be made, and the detection of characteristics such as data, temperature and other terms is improved.

Abstract: A system for transferring data in a single clock cycle between a digital signal processor (DSP) and an external memory unit and method of same. The system includes a data transfer element coupled between the external memory unit and the DSP, where the data transfer element is adapted to transfer the data between the external memory unit and the DSP in a single clock cycle. In one embodiment, the data transfer element is a coprocessor including a plurality of latch devices coupled to buses between the DSP and the memory unit. A first set of data are transferred from a first memory unit (e.g., from either the DSP internal memory unit or the external memory unit, depending on the direction of the data transfer) into the coprocessor during a first clock cycle and out of the coprocessor to a second memory unit in a second clock cycle occurring immediately after the first clock cycle.

Abstract: A system and apparatus is provided for preventing damage to gate oxide due to ultraviolet radiation associated with semiconductor processes. Included is a substrate and a gate formed on the substrate. The gate includes a gate material layer and a gate oxide layer stacked on the substrate. A pair of spacers are situated on opposite sides of the gate. Deposited over the gate and the spacers is an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate. Finally, at least one metal and intermetal oxide layer is positioned over the ultraviolet radiation blocking material. In an alternate embodiment, instead of the ultraviolet radiation blocking material being deposited over the gate and the spacers, the spacers are constructed from an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate.

Abstract: Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.