Abstract: A communication device and a method for transmitting data in wireless local area networks is provided. The device and method are deployed in networks in which the data information elements include an element identification part, a length statement part and an information part. The device and method enable a broad range of data transmission rates and are full compatible with communicating units operating according to previous modes in which a first data transmission rule defines the acceptable range of values of element identification parts. In the method, a second data transmission rule is implemented in at least one of the communicating units to extend the acceptable range of values of element identifications. The range of values is extended so that a second standard portion of the element identification part marks the information element as a second information element.

Abstract: To control a baseband processor within a wireless network, data transmission rules are implemented in respective hosts for first and second communicants, which guarantee data transmission there between according to the rules. Data packets are communicated over electromagnetic signal paths by high frequency transceiver of a WLAN card connected to the host by a WLAN card interface. A baseband processor, on the WLAN card, prepares data packets according to the rules. The first and/or second communicants are controlled by a protocol module in the host, using hardware driver in the host, avoiding WLAN card interface. WLAN card hardware operates solely according to conditions and restrictions of a data transmission rule agreed between protocol module and baseband processor, independent of conditions and restrictions of operating system and WLAN card interface and hence, a functional region is generated in the WLAN card with hardware and software interfaces, implemented according to the rule.

Abstract: A tape guide in which the corner geometry between the flanges and the hub prevents the tape from abruptly bumping the flange and in which the corner is coated with a very hard wear resistant material such as titanium aluminum nitride, tungsten carbide, silicon nitride, chromium nitride or diamond like carbon.

Abstract: A mixed-signal CMOS integrated semiconductor device exhibits reduced substrate noise coupling between digital and analog circuit functions using selectively formed isolated, high-impurity buried regions between substrate and epitaxial layers. The impedance within the high-impurity regions is relatively lower than the impedance between high-impurity regions, thereby reducing noise-induced potentials, and latchup, within high-impurity regions and noise-induced currents between high-impurity regions. An attenuation network is effectively formed in the semiconductor device layers to reduce noise coupling, the impedance within the high-impurity region acting as the pi attenuation network shunt path. High-impurity regions are formed by selectively diffusing or implanting impurities into bulk lightly-doped, silicon substrate layer prior to growing an epitaxial layer. The high-impurity regions, substrate and epitaxial layers are all of the same conductivity type.

Abstract: A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear.

Abstract: The present invention embodiment comprises an arrangement of integrated circuits with a UART device that is configurable to operate in a power-reduced mode while the clock frequency of serial data communication remains constant. In one example embodiment, an arrangement of a plurality of integrated circuit devices includes a first integrated circuit device driven by a first clock signal at a first clock rate. The arrangement contains a parallel data bus coupled to communicate with the first integrated circuit device in response to the first clock signal. The arrangement also includes a universal asynchronous receiver/transmitter (UART) chip with a serial communication circuit adapted to communicate serial data at a second rate defined by a second clock signal. The UART chip also encompasses a parallel bus interface circuit responsive to the first clock signal and adapted to pass data between the parallel data bus and the serial communication circuit.

Abstract: A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.

Abstract: A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.

Abstract: A configurable universal asynchronous receiver/transmitter (UART) facilitates efforts to upgrade UART functionality in the field and replace older UART devices. In one example embodiment, an integrated circuit includes a universal asynchronous receiver/transmitter configured and arranged to operate in one of a plurality of modes, with each mode being selectable in response to mode-selecting data. The integrated circuit device includes an interface circuit electrically connected to the universal asynchronous receiver/transmitter and adapted to present the mode-selecting data to the universal asynchronous receiver/transmitter. The integrated circuit device also includes a selection circuit adapted to enable the mode-selecting data to pass from the interface circuit to the universal asynchronous receiver/transmitter.

Abstract: An integrated circuit arrangement is reconfigurable in the field to operate in one of a plurality of modes, including a test mode, in response to mode-selecting codes presented via a temporary register in the circuit. In one example embodiment, an arrangement of integrated circuits includes a reconfigurable integrated circuit configured and arranged to operate in one of a plurality of modes. The reconfigurable integrated circuit includes a register adapted to store data for temporary use, with each operating mode of the reconfigurable circuit being selectable in response to mode-selecting data code. An interface circuit is electrically connected to the reconfigurable integrated circuit and is adapted to present the mode-selecting data code to the reconfigurable integrated circuit. A selection circuit is adapted to enable the interface circuit to pass mode-selecting data to the reconfigurable integrated circuit.

Abstract: Signal correction in a bipolar transistor circuit having a base-emitter voltage and a non-linear output signal corresponding to a detectable characteristic is improved by correcting non-linearity in the signal at third and/or higher-orders. According to an example embodiment of the present invention, the output of the transistor is corrected as a function of the base-emitter voltage, the non-linear output signal and a generated non-linearity. The generated non-linearity is adapted to cancel the non-linearity of the non-linear output signal when added thereto. Various implementations of the present invention are applicable to a variety of applications, each of which may have selected characteristics that are accounted for by the generated non-linearity, which is selectively adapted for each particular application. In this manner, third and higher-order corrections can be made, and the detection of characteristics such as data, temperature and other terms is improved.

Abstract: The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset signal generator is coupled to a clock module having an external clock reference and to each of the peripheral devices. A reset clock signal having the reference clock frequency is sent to each of the peripheral devices via clock outputs at the clock module. A synchronization module at each of the peripheral devices is adapted to synchronize the reset signal among all peripheral devices using the clock signal. The clock module holds the reset clock signal for a selected amount of time, and then releases the signal from the external clock.

Abstract: The reliability and operability of semiconductor devices is improved using a circuit arrangement and method that improves the ability to manage data storage and retrieval. According to one example embodiment of the present invention, a memory device includes a dynamically configurable page table having a plurality of pages. The page table is dynamically configurable to at least two organizations, and each page includes a multitude of memory storage locations adapted to store data. A controller is adapted to track memory requests and to configure the page table to one of the at least two organizations during a memory refresh cycle, wherein the configuration is effected in response to the tracked memory requests. In this manner, the page table can be adapted to improve the effectiveness and speed of data storage and retrieval.

Abstract: A pulse-width modulation technique uses a counter load value that alternates between a duty-cycle defining value and its complement. In one embodiment, a pulse-width modulated signal is produced as a function of a control signal used to reload the counter in response to the counter reaching an overflow threshold value. This approach includes storing the counter load value and counting relative to a logic circuit output value which corresponds to either the load value or its complement. The counting is reinitiated using the logic circuit output in response to the counter reaching an overflow threshold value. A specific example application of the above type of PWM approach is directed to implementation in otherwise conventional up/down digital counters such as exists in 80C51-type microcontrollers.

Abstract: A system for transferring data in a single clock cycle between a digital signal processor (DSP) and an external memory unit and method of same. The system includes a data transfer element coupled between the external memory unit and the DSP, where the data transfer element is adapted to transfer the data between the external memory unit and the DSP in a single clock cycle. In one embodiment, the data transfer element is a coprocessor including a plurality of latch devices coupled to buses between the DSP and the memory unit. A first set of data are transferred from a first memory unit (e.g., from either the DSP internal memory unit or the external memory unit, depending on the direction of the data transfer) into the coprocessor during a first clock cycle and out of the coprocessor to a second memory unit in a second clock cycle occurring immediately after the first clock cycle.

Abstract: A system and apparatus is provided for preventing damage to gate oxide due to ultraviolet radiation associated with semiconductor processes. Included is a substrate and a gate formed on the substrate. The gate includes a gate material layer and a gate oxide layer stacked on the substrate. A pair of spacers are situated on opposite sides of the gate. Deposited over the gate and the spacers is an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate. Finally, at least one metal and intermetal oxide layer is positioned over the ultraviolet radiation blocking material. In an alternate embodiment, instead of the ultraviolet radiation blocking material being deposited over the gate and the spacers, the spacers are constructed from an ultraviolet radiation blocking material for preventing the ultraviolet radiation from damaging the gate oxide layer of the gate.

Abstract: An approach for impedance matching a transmission line includes using the actual line impedance. According to one example embodiment, the impedance of a line connecting first and second nodes is calibrated by first driving the line to a steady-state voltage using a first current having a magnitude greater than zero, driving the current to a zero magnitude from the first node and therein inducing a voltage transient. The resultant voltage level on the line at the first node is then measured and analyzed relative to a reference voltage. The result of the comparison is then used to adjust the conductance at the second node.

Abstract: For use with sub-micron CMOS technologies, a gate etch process improves control of the etch profile. Gate stacks utilize N-type or P-type doped amorphous or poly silicon to enhance device performance. However, the different etching characteristics of the N-type versus the P-type amorphous or poly silicon material can result in a localized breakthrough of the underlying thin gate oxide adjacent to the edge of the gate stack, especially in the N doped active regions. According to one example embodiment, this localized breakthrough (“microtrenching”) is avoided by building the gate stacks with undoped amorphous or poly silicon to the desired configuration, masking the gate stacks with a dielectric layer, planarizing the dielectric layer and then implanting the N-type or P-type species into the selected gate stack.

Abstract: Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.

Abstract: The performance of the main regulatory transistor of an on-chip voltage regulator circuit is enhanced when the main transistor is appropriately biased during start up. In an example embodiment, a voltage regulator circuit includes a thin gate oxide transistor as the main regulatory transistor and an operational amplifier that is referenced to a midlevel operating voltage. During start-up, the potential voltage difference is large enough to necessitate the disconnection of the main transistor from the operational amplifier. A voltage divider ladder circuit is used to maintain the gate voltage of the main transistor at the midlevel voltage while a smaller thick gate oxide transistor is used to maintain loop stability and to withstand voltage transients.