Abstract: The invention provides ESD protection for IC's while isolating the different power supplies from one another. A network in the IC has a plurality of circuit cells through which the IC receives power. Each circuit cell provides localized electrostatic discharge protection. With each circuit cell coupled to a global node through a dual current direction coupling network and with portions of the global node physically separating the circuit cells, any noise, interference, or stray ESD current generated by a circuit cell is shunted away from other circuit cells to the global node. An off-chip ground connection coupled to the global node provides a destination for this noise or interference.

Abstract: An improved balanced mixer is provided for use in radio communication devices. The improved balanced mixer comprises a known Gilbert type mixer, a transconductance amplifier, a signal splitter, and a dual feedback structure from the pre-amplifier output to the input ports, thereby providing better linearity, that is, better input third order intercept point (IIP3), and improved impedance matching, without increasing the circuit noise figure.

Abstract: A method and an apparatus relating to a PLL circuit for frequency synthesizer applications. By using a composite PFD large and small phase variations between a reference signal and the divider output are compensated for. The composite phase frequency detector (PFD) has both a digital phase frequency detector (digital PFD) and an analog phase detector (analog PD) with the digital PFD compensating for large phase differences and the analog PD compensating for smaller phase differences. The PLL automatically chooses between these two components in the composite PFD by controlling the pulse width of the divider output. This is accomplished by synchronizing the dead zone of the digital PFD with the active pulse width of the divider output and by similarly synchronizing the phase detector window of the analog PD to be within both the dead zone of the digital PFD and the active pulse width of the divider output.

Abstract: A complex filter minimizing mismatch error by averaging the mismatch error by integrating the real and imaginary input signals using the same integrator. A further advantage is that, as compared to known devices, the complex filter uses fewer number of components thereby reducing the consumed power. The complex filter may be used in a complex bandpass sigma-delta modulator, thereby increasing the performance of the sigma-delta modulator. The complex filter used in a sigma-delta modulator analog to digital converter increases performance of the analog to digital conversion since the mismatch noise is minimized. The complex bandpass sigma-delta modulator analog to digital converter include any number of complex filter stages.

Abstract: A method and apparatus for dynamically generating multiple level decision thresholds of an M-ary demodulated signal for decoding the signal. The threshold values are obtained by obtaining the maximum and minimum peak values of the demodulated M-ary signal, averaging these peak values and subsequently processing these averaged values to establish the threshold for the particular M-ary signal. Infinite impulse response filters may be advantageously used in the averaging process and these filters may be preloaded with maximum and minimum peak values such that decision threshold levels may be generated immediately after receiving the M-ary demodulated signal.

Abstract: A delta-sigma modulator having a dead-zone quantizer and an error shaping digital filter clocked by a signal which is periodic at the frequency of the reference. A dead-zone quantizer provides quantization of a high resolution digital word to a low resolution digital word with three or a higher odd number of possible output levels and with an output of zero for an input near the center of the normal input range. The delta-sigma modulator is used in a fractional-N divider. The fractional-N divider is used in a fractional-N frequency synthesizer.

Abstract: An apparatus and method to obtain a high Q, narrowband active filter with high gain suitable for an integrated circuit implementation. The high Q is achieved via active feedback with an amplitude control loop. The frequency control of the active filter is achieved by means of a frequency locked loop. Both control loops compare the thermal noise of the active filter itself to voltage and frequency references to achieve the stable operating point. Control loops are normally slow relative to the transmitted data, hence avoiding the data altering the operating point of the filter.