Abstract: An electronic package and a method for fabricating the same are provided. The method includes bonding a portion of an inactive surface of an electronic component to a thermal conductive layer of a heat dissipating element, encapsulating the electronic component and the thermal conductive layer with an encapsulant, and forming a circuit structure on the encapsulant and electrically connecting the circuit structure to the electronic component. Since the heat dissipating element is bonded to the electronic component through the thermal conductive layer, the heat dissipating effect of the electronic package is improved.

Abstract: An integrated driving module with energy conversion function includes a patterned conductive circuit layer, an integrated electromagnetic induction component layer, a second dielectric layer, an embedded electrical component and a conductive component. The integrated electromagnetic induction component layer, which has a plurality of conductive coil layer, a plurality of conductive connecting component and a first dielectric layer, is disposed on the patterned conductive circuit layer. The conductive coil layers are stacked. Each conductive connecting component is electrically connected between the two conductive coil layers and between the corresponding conductive coil layer and the patterned conductive circuit layer. The first dielectric layer covers the conductive coil layers and the conductive connecting components. The second dielectric layer covers the patterned conductive circuit layer.

Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device disposed in the molding compound body, the first circuit device having a first terminal at a top of the first circuit device; a first conductive via formed in the molding compound body and connected to the first terminal; a second circuit device disposed in the molding compound body, the second circuit device having a second terminal at a top of the second circuit device; a second conductive via formed in the molding compound body and connected to the second terminal; and a redistribution layer with a conductive wire formed on the molding compound body, the conductive wire connecting the first conductive via and the second conductive via; wherein the first and second terminals are respectively located at different depths of the molding compound body.

Abstract: This disclosure provides a package structure and its fabrication method. The package structure includes: a conductive pattern layer having a bump region and a wiring region, the bump region comprising a plurality of conductive bumps and a first dielectric material surrounding the plurality of conductive bumps, the wiring region comprising a plurality of first conductive wires and a second dielectric material covering and surrounding the plurality of first conductive wires; a circuit device with a plurality of connecting terminals disposed on the bump region, each of the connecting terminals corresponding with one of the conductive bumps; an insulation sealant formed on the second dielectric material and around sidewalls of the circuit device; and a third dielectric material covering the circuit device and the wiring region.

Abstract: A package structure is provided, which includes: a first polymer layer with a first surface; a second polymer layer with a second surface on the first polymer layer; a circuit device with opposing third and fourth surfaces, the circuit device disposed on the second polymer layer and with multiple metal pads on the fourth surface; a first high-filler dielectric layer enclosing the circuit device and the second polymer layer and covering the first polymer layer; a first conductive wiring formed on the first high-filler dielectric layer; a first conductive passage formed in the first high-filler dielectric layer and connecting the first conductive wiring to the metal pads; a second high-filler dielectric layer enclosing the first conductive wiring and covering the first high-filler dielectric layer; and a second conductive passage formed in the second high-filler dielectric layer and connecting the first conductive wiring to an external circuit.

Abstract: A sensor package includes a sensor, an encapsulation layer, a redistribution layer, a photo-imageable dielectric (PID) layer and via plugs. The encapsulation layer exposes the active surface of the sensor, and the top surface of the encapsulation layer is coplanar with the active surface of the sensor. The redistribution layer covers the top surface of the encapsulation layer and the active surface of the sensor. The PID layer covers the redistribution layer, the encapsulation layer and the active surface of the sensor. The via plugs are disposed around the sensor and through the encapsulation layer. The via plugs are electrically connected to the redistribution layer and the active surface of the sensor. The cross section of the via plug at the top surface of the encapsulation layer has a first hole diameter, and the cross section of the via plug at the bottom surface of the encapsulation layer has a second hole diameter. The first hole diameter is less than the second hole diameter.

Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate includes: a dielectric body; a first circuit device disposed in the dielectric body, the first circuit device comprising a first terminal and a second terminal at a top of the first circuit device; a second circuit device disposed in the dielectric body, the second circuit device comprising a third terminal at a top of the second circuit device; a first conductive pillar formed in the dielectric body and connected to the first terminal; a first bonding wire connecting the second terminal and the third terminal; and a redistribution layer comprising a first conductive wire formed on the dielectric body, the conductive wire connected to the first conductive pillar.

Abstract: This disclosure provides a package substrate which includes: a first conductive layer having a first conductive area and a second conductive area; a package unit layer disposed on the first conductive layer and including a first circuit device having a first terminal connected to the first conductive area and a second terminal connected to the second conductive area, a first conductive pillar connected to the first conductive area, and an encapsulant material; and a second conductive layer disposed on the package unit layer and having a first metal wire connected to the first conductive pillar.

Abstract: A packaging substrate is provided, which includes: an insulating layer; a plurality of conductive bumps formed on the insulating layer, wherein each of the conductive bumps has a post body exposed from the insulating layer and a conductive pad embedded in the insulating layer, the post body being integrally formed with and less in width than the conductive pad; and a plurality of conductive posts disposed on the conductive pads and embedded in the insulating layer. As such, a semiconductor chip can be bonded to the packaging substrate through the conductive bumps. The present disclosure further provides a method for fabricating the packaging substrate.

Abstract: A substrate structure includes a metal substrate, a first connection layer, a second connection layer, a dielectric material layer, a metal core layer and an internal component. The first and second connection layers are disposed on a surface of the metal substrate. The metal core layer having an opening is disposed on a surface of the first connection layer. The internal component having a plurality of electrode pads is disposed on a surface of the second connection layer and in the opening of the metal core layer. The dielectric material layer is disposed on the surface of the metal substrate. The first and second connection layers, the metal core layer and the internal component are partially covered with the dielectric material layer. The metal core layer is electrically connected to one of the electrode pads via the first and second connection layers and the metal core layer.

Abstract: A method and apparatus for growing a semiconductor crystal include pulling the semiconductor crystal from melt at a pull speed and modulating the pull speed by combining a periodic pull speed with an average speed. The modulation of the pull speed allows in-situ determination of characteristic temperature gradients in the melt and in the crystal during crystal formation. The temperature gradients may be used to control relevant process parameters that affect morphological stability or intrinsic material properties in the finished crystal such as for instance the target pull speed of the crystal or the melt gap, which determines the thermal gradient in the crystal during growth.

Abstract: An improvement to a method and an apparatus for growing a monocrystalline silicon ingot from silicon melt according to the CZ process. The improvement performs defining an error between a target taper of a meniscus and a measured taper, and translating the taper error into a feedback adjustment to a pull-speed of the silicon ingot. The conventional control model for controlling the CZ process relies on linear control (PID) controlling a non-linear system of quadratic relationship defined in the time domain between the diameter and the pull-speed. The present invention transforms the quadratic relationship in the time domain between the diameter and the pull-speed into a simile, linear relationship in the length domain between a meniscus taper of the ingot and the pull-speed.

Abstract: The present invention provides a method and apparatus for controlling the growth of a silicon ingot in which the diameter of the growing silicon ingot can be accurately measured. A camera captures an image of the interface ring between the growing silicon ingot and the silicon melt. An image processor extracts local intensity maxima from the captured image, which are then digitized into an image data which comprises attributes of the pixels forming the local intensity maxima. An analyzer statistically analyzes the image data to derive parameters of an equation statistically simulating the interface ring. A probabilistic filter conducts the statistical analysis on the equation in which the respective pixels are weighted by their weight factors. The weight factor functions to attenuate the effect of noises caused by pixels which do not represent the interface ring.

Abstract: A system and method correct crystal pulling motor speed deviations in a crystal pulling mechanism. In a first embodiment, a processor implements a tracking filter by estimating new filter state based on previous state and the since-then-travelled nominal distance, and then updating the filter state based on estimation error and filter gains which are also functions of the travelled nominal distance. In a second embodiment, a harmonic tracking filter suppresses residual harmonic modulation and allows a short time constant. Rapid variations of pulling speed may thus be corrected.

Abstract: A method and apparatus for growing a semiconductor crystal include pulling the semiconductor crystal from melt at a pull speed and modulating the pull speed by combining a periodic pull speed with an average speed. The modulation of the pull speed allows in-situ determination of characteristic temperature gradients in the melt and in the crystal during crystal formation. The temperature gradients may be used to control relevant process parameters that affect morphological stability or intrinsic material properties in the finished crystal such as for instance the target pull speed of the crystal or the melt gap, which determines the thermal gradient in the crystal during growth.

Abstract: An improvement to a method and an apparatus for growing a monocrystalline silicon ingot from silicon melt according to the CZ process. The improvement performs defining an error between a target taper of a meniscus and a measured taper, and translating the taper error into a feedback adjustment to a pull-speed of the silicon ingot. The conventional control model for controlling the CZ process relies on linear control (PID) controlling a non-linear system of quadratic relationship defined in the time domain between the diameter and the pull-speed. The present invention transforms the quadratic relationship in the time domain between the diameter and the pull-speed into a simile, linear relationship in the length domain between a meniscus taper of the ingot and the pull-speed.

Abstract: Straight tracks are formed in a first direction on a base. The top surface of a platform is formed so as to be flat to mount a wafer having an Ori-Fla, and the platform is moved in the first direction by being engaged with the straight tracks via engagement means. A block having a flat face against which the Ori-Fla of the wafer abuts and which is parallel with the first direction is installed with a first clearance L being provided with the straight track in a second direction perpendicular to the first direction. Wafer fixing means for fixing the wafer in a state in which the wafer is mounted on the platform is provided in the platform, and a measurement device having a probe opposed to the straight track and capable of being displaced in the second direction is installed on the base with a second clearance M being provided with the block in the first direction. When a clearance between the tip end of the probe and the straight track is taken as N, the relationship of 0 ?m<L?N?100 ?m exists.

Abstract: A process for effectively reducing reactivity of a surface of a semiconductor substrate is described. The process includes: (1) oxidizing in an oxidizing environment the semiconductor substrate surface, the semiconductor substrate having a dopant concentration profile that extends across a depth of the semiconductor substrate; and (2) annealing the semiconductor substrate surface in an inert gas environment, wherein the oxidizing and the annealing of the semiconductor substrate surface are performed at a temperature that is sufficiently low to substantially preserve the dopant concentration profile in the semiconductor substrate. A surface passivation apparatus is also described. The apparatus includes: a heating source for heating a substrate surface; an ozone generator; and a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition, wherein the ozone generator is configured to produce ozone within the chamber using the gas composition.

Abstract: A method and system for conducting multiple access simultaneous telephone communications in full duplex either over the power lines of a building or using RF transmission. It employs a combination of multiple access techniques selected from among the following: time division, code division, and frequency division. The following features result: a) security coding to prevent unauthorized access and eavesdropping, b) multiple simultaneous conversations through identical and closely coupled transmission media, c) non-interference to other communications systems and users, and d) processing gain for operating in noisy environments.