Abstract: A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface in the cavity of a board; filling the cavity with an adhesive for fixing the chip; forming a solder mask on the active surface of the chip and the surface of the metal carrier board at the same side, wherein the solder mask has a plurality of openings to expose the electrode pads of the chip; forming a built-up structure on the solder mask and the exposed active surface of the chip in the openings; and removing the metal carrier board. In this method the metal carrier board can support the built-up structure to thereby avoid warpage.

Abstract: A package structure includes a first carrier board provided with a through hole, at least a filling hole in communication with the through hole, a semiconductor chip received in the through hole, and a fastening member disposed in the filling hole and abutting against the semiconductor chip so as to secure the semiconductor chip in position, thereby preventing the semiconductor chip in the through hole from displacement under an external force.

Abstract: A carrier structure embedded with semiconductor chips is disclosed, which comprises a core board and a plurality of semiconductor chips mounted therein. The core board comprises two metal plates between which an adhesive material is disposed. An etching stop layer is deposited on the both surfaces of the core board. Pluralities of cavities are formed to penetrate through the core board. The semiconductor chips each have an active surface on which a plurality of electrode pads are disposed, and those are embedded in the cavities and mounted in the core board. An etching groove formed on the core board between the neighboring semiconductor chips is filled with the adhesive material. The present invention avoids the production of metal burrs when the carrier structure is cut.

Abstract: An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

Abstract: A packaging substrate structure with electronic components embedded therein and a method for manufacturing the same are disclosed. The packaging substrate structure comprises: a core board; a built-up structure disposed on at least one surface of the core board, wherein the built-up structure has a plurality of conductive pads and an electronic component-disposing part on the surface thereof; a solder mask disposed on the surface of the built-up structure, where the solder mask has a open area to expose the electronic component-disposing part and a plurality of openings to expose the conductive pads of the built-up structure; and an electronic component disposed on the electronic component-disposing part and in the open area. Accordingly, the packaging substrate disclosed by the present invention exhibits enhanced electrical performance and product reliability.

Abstract: Method for making a coreless packaging substrate are disclosed in the present invention. The coreless packaging substrate is made by first providing a metal adhesion layer having a melting point lower than that of the substrate, and removing a core board connected with the substrate therefrom through melting the metal adhesion layer. In addition, the disclosed packaging substrate further includes a circuit built-up structure of which has the electrical pads embedded under a surface. The disclosed packaging substrate can achieve the purposes of reducing the thickness, increasing circuit layout density, and facilitating the manufacturing of the substrate.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: An electrically connecting terminal structure of a circuit board and a manufacturing method thereof are disclosed.

Abstract: A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer.

Abstract: A package structure having a semiconductor chip embedded therein and a method of fabricating the same are disclosed. The package structure comprises: an aluminum oxide composite plate and a semiconductor chip. The aluminum oxide composite plate is formed by a stack consisting of an adhesive layer placed in between two aluminum oxide layers. The semiconductor chip having an active surface a plurality of electrode pads disposed thereon can be embedded and secured in the aluminum oxide composite plate. The present invention also comprises a method of fabricating the above-mentioned package structure. The present invention provides an excellent package structure, which can decrease the thickness of the package structure and make the package structure having characteristics of high rigidity and enduring tenacity at the same time.

Abstract: A conductive bump structure of a circuit board and a method for forming the same are proposed. A conductive layer is formed on an insulating layer on the surface of the circuit board. A first resist layer is formed on the conductive layer and a plurality of first openings is formed in the first resist layer to expose the conductive layer. Then, a patterned trace layer is electroplated in the first openings and a second resist layer is covered on the circuit board with the patterned trace layer. Second openings are formed in the second resist layer to expose part of the trace layer to be used as electrical connecting pads. Thereafter, metal bumps are electroplated in the second openings and the surface of the circuit board is covered with a solder mask. A thinning process is applied to the solder mask to expose the top surface of the metal bumps. Afterwards, an adhesive layer is formed on the surface of the metal bumps exposing out of the solder mask.

Abstract: A semiconductor package substrate includes a main body with a surface having a first circuit layer thereon and a dielectric layer covering the first circuit layer, with a plurality of vias on a portion of the first circuit layer; a plurality of first conductive vias disposed in the vias; a plurality of first electrically connecting pads on the first conductive vias and completely exposed on the dielectric layer having no extending circuits for a semiconductor chip to be mounted thereon, the first electrically connecting pad being electrically connected to the first circuit layer of the first conductive via; and an insulating protective layer disposed on the main body with an opening for completely exposing the first electrically connecting pads, whereby the circuit layout density is increased without disposing circuits between the electrically connecting pads.

Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

Abstract: A packaging substrate is disclosed, which comprises: a substrate body, wherein a surface thereof has a plurality of conductive pads and a solder mask disposed on the surface and having a plurality of openings to expose the conductive pads; dielectric rings disposed on the inner walls of the openings and extending to parts of the surface of the solder mask surrounding the openings; and metal bumps disposed in the openings and on the conductive pads exposed thereby, and combined with the dielectric rings.

Abstract: An electrical connection element of packaging substrate is disclosed. Wherein a plurality of conductive pads and a solder mask are formed on the surface of the packaging substrate, and a plurality of openings is formed in the solder mask to expose the conductive pads covered there beneath. The electrical connection element formed on the conductive pad comprises a core layer, a first covering layer and a second covering layer. The first covering layer covers the core layer, and the density of the first covering layer is higher than the density of the core layer. The second covering layer covers the first covering layer.

Abstract: A method for fabricating a conductive bump structure of a circuit board is disclosed. The circuit board with a plurality of electrical connection pads is provided. An insulating protective layer and a resist layer are successively applied on the circuit board, wherein openings are formed in the layers at positions corresponding to the pads to expose the pads. Then, a conductive layer is formed on surfaces of the resist layer and openings, and a metal layer is formed on the conductive layer via electroplating and filled in the openings. Subsequently, the metal layer and conductive layer formed on the resist layer are removed via thinning, so as to form metal bumps on the pads. After the resist layer is removed, the metal bumps are covered by an adhesive layer to form a conductive bump structure for electrically connecting the circuit board to the external electronic component.

Abstract: A circuit board structure having a capacitor array and an embedded electronic component and a method for fabricating the same are proposed. Two carrier boards and a high dielectric constant material layer are provided, wherein the carrier boards have electronic components embedded therein and one surface of each carrier board has a plurality of electrode plates. The two carrier boards are laminated with the dielectric constant material layer interposed between them. The electrode plates on the surfaces of the carrier boards are opposite to each other across the high dielectric constant material layer to constitute a capacitor array. Therefore, the capacitor assembly for design of electronic devices is provided.

Abstract: Conductive structures for electrically conductive pads of a circuit board and fabrication method thereof are proposed. The fabrication method includes: providing a circuit board with a plurality of first, second and third electrically conductive pads; forming first and second conductive layers on the circuit board; forming first and second resist layers respectively on the first and second conductive layers, the resist layers having a plurality of openings for exposing the conductive layers on the pads; forming a metal layer in the openings of the first and second resist layers; and forming a first connecting layer on the metal layer; forming third and fourth resist layers on the first and second resist layers respectively, the third resist layer having a plurality of openings for exposing the first connecting layer on the metal layer on the second electrically.

Abstract: Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads.

Abstract: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection pads. The conductive bumps are formed on the electrical connection pads of at least one of the circuit boards. The adhesive layer is formed between the circuit boards such that a portion of the adhesive layer between the conductive bumps and the electrical connection pads, or between the opposing conductive bumps, forms a conductive channel and thereby forms an electrical connection between the circuit boards.