Abstract: A method of manufacturing a coreless packaging substrate is disclosed. The method can produce a coreless packaging substrate which comprises: at least a built-up structure having a first solder mask and a second solder mask, wherein a plurality of openings are formed in the first and second solder mask to expose the conductive pads of the built-up structure; and a plurality of solder bumps as well as solder layers formed on the conductive pads. Therefore, the invention can produce the coreless packaging substrate with high density of circuit layout, less manufacturing steps, and small size.

Abstract: A method of embedding a semiconductor chip in a support plate and an embedded structure thereof are proposed. A first dielectric layer having a reinforced filling material is provided, and a semiconductor chip is mounted on the first dielectric layer. A support plate having an opening and a second dielectric layer having a reinforced filling material are provided. The first dielectric layer mounted with the semiconductor chip, the support plate, and the second dielectric layer are pressed together, such that the semiconductor chip is received in the opening of the support plate, and the dielectric layers fill in a gap between the semiconductor chip and the opening of the support plate. The reinforced filling material of the dielectric layers can maintain flatness and consistency of the semiconductor chip embedded in the support plate, and fine circuits can be fabricated on the support plate by build-up and electroplating processes.

Abstract: A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.

Abstract: A method for fabricating a core circuit board having passive components, such as resistors, capacitors and inductors, is disclosed, which can be used to construct a multilayer circuit board having embedded passive components. In making such as a core circuit board, a resistive film which is a continuous or non-continuous is first formed on one side of a conductive foil. Two such conductive foils are laminated onto a high dielectric layer. The electrodes for various passive components or spiral coils for the inductive components and electrical circuit pattern are finally made on the same conductive foils simultaneously. Finally, a core circuit board having passive components for further making a multilayer circuit board is thus constructed.

Abstract: The present invention discloses a substrate within a Ni/Au structure electroplated on electrical contact pads and a method for fabricating the same. The method comprises: providing a substrate with a circuit layout pattern and forming a conducting film on the surface of the substrate; depositing a first photoresist layer within an opening on said electrical conducting film surface to expose a portion of said circuit layout pattern to be electrical contact pads; removing the exposed conducting film uncovered by the first photoresist layer; depositing a second photoresist layer, covering the conducting film exposed in the openings of the first photoresist layer; electroplating Ni/Au covering the surface of the electrical contact pads; removing the first and second photoresists, and the conducting film covered by the photoresists; depositing solder mask on the substrate within an opening to expose said electrical contact pads.

Abstract: BGA substrate with direct heat dissipating structure The present invention discloses a structure of BGA substrate with direct heat-dissipating structure, said structure comprising: a heat spreader, no less than one insulating resin layer, an upper circuit layer, a lower circuit layer, and a plurality of electrically-conducting plugs. The heat spreader comprises a body part, a loading part, and a junction part. The loading part is the upper region of heat spreader. The junction part is the lower region of the heat spreader. The periphery of said junction part extends outward for forming a protruding edge. The body part is embedded into the central region of the substrate. The upper circuit layer is formed on the surface of said resin layer. The lower circuit layer is formed on lower surface of said resin layer and comprises a plurality of solder pads. The upper and lower circuit layers are conducted by electrically conductive plugs.

Abstract: Disclosed is a structure of substrate and a fabricating method for IC (integrated circuit) chip package. Selected areas of the copper plate are etched for forming the plural conducting columns, and then an insulating layer is laminated to said copper plate to make said conducting columns embedded into said insulating layer. After portions of said insulating layer are removed for forming the plural blind vias each corresponding to exposed conducting columns, both said plural blind vias and the upper surface of said insulating layer are plated with a copper layer. An upper circuit layer and a lower circuit layer formed by etching said copper layer and said copper plate are covered with solder mask layers for protecting the substrate.