Abstract: An analog to digital converter converts an analog input signal to at least two digital output signals as follows. An analog feedback signal is subtracted from the analog input signal to produce a difference signal. The difference signal, then, is integrated to produce an integrated signal which is quantized to produce the digital output signals in response to respective control signals each having a predetermined frequency and being offset in phase from each other. Finally, the digital output signals are converted into the analog feedback signal. Such analog to digital converter uses components operating at a lower frequency than the sampling frequency fs without loss of dynamic range.
Abstract: A symmetrical loading and current supply arrangement is described for a differential-type logic means, and symmetrical voltage swings are thereby achieved in the logic output. In a preferred arrangement the output voltages are self-aligned to a CMOS level which facilitate conversion of the differential-type output to CMOS signals.
Type:
Grant
Filed:
April 30, 1998
Date of Patent:
September 19, 2000
Assignee:
Phoenix VLSI Consultants LTD.
Inventors:
Andrew James Pickering, Giuseppe Surace
Abstract: A ring oscillator comprises a ring of delay stages in which the output of each stage is input to the next stage in the ring. Tuning of the oscillation frequency of the oscillator is achieved by additionally taking outputs from delay stages elsewhere in the ring as one or two secondary inputs to each delay stage and mixing this or these in variable proportions with the primary input.
Type:
Grant
Filed:
September 10, 1997
Date of Patent:
December 21, 1999
Assignee:
Phoenix Vlsi Consultants, Ltd.
Inventors:
Andrew James Pickering, Ian Charles Wood
Abstract: A bipolar transistor module which can be implemented into existing CMOS processes without the use of buried layers of epitaxy is described. The transistor makes use of a synthesis of new ideas to achieve high performance. Extended polysilicon electrodes (2,4,6) are utilised to reduce device dimensions and a compatible well is described which maintains a p-channel MOS transistor electrical characteristics whilst lowering the collector series resistance.