Abstract: The present invention relates to a self-diagnostic apparatus capable of improving safety of a device under test (DUT) by analyzing a characteristic change of a DUT, such as a semiconductor, a circuit module, or a system, in a safe operating region over time and allowing a regular test and a periodic test to be performed even while the DUT is running.

Abstract: Provided is a measuring method for testing a device under test (DUT) having a plurality of terminals and, particularly, to a means for measuring the functions and performance of various electronic devices in which an electronic circuit such as that in an electronic device, a semiconductor element, a circuit module, and a circuit board is mounted, and to: a method by which a processor supports measurement with software such that unit costs can be reduced to be lower than those of conventional means operating with various, high-cost hardware; and a device using the same.

Abstract: The present invention relates to a self diagnostic apparatus for an electronic device, which includes a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores which perform arithmetic operations, a function test expected value corresponding to a function test according to the test function code, a design for test (DFT) test code, a DFT test expected value corresponding to a DFT test according to the DFT test code, and a non-test function code for a general arithmetic operation or an operation of the DUT; a test data storage configured to store test data including a DFT test code result value which is a result of the DFT test according to the DFT test code, a test function code result value which is a result of the function test according to the test function code, and a non-test function code result value which is a result of the function test according to the non-test function code; and a safety region test controller configured to sele

Abstract: Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.

Abstract: A current measurement apparatus comprises: a capacitor connected in parallel to a signal terminal of a device under test (DUT); a test pattern generation apparatus generating a test pattern to operate the DUT; and a measurement module connected to one end of the capacitor. The measurement module comprises: an input/output (I/O) buffer increasing or reducing an amount of charges of the capacitor and outputting a signal corresponding to an output logic value according to a voltage of the one end of the capacitor; a time measurer measuring an arrival time which it takes for the voltage of the one end of the capacitor to reach a second voltage from a first voltage; and a controller controlling the i/o buffer and the time measurer to measure the arrival time and controlling such that a value of a current related to an inspection of a DUT is measured using the arrival time.