Abstract: The present invention discloses a digital leakage canceling device of an RFID reader and a method thereof. The device includes: a coupling unit configured to couple an antenna signal and a power amplifier signal; an RF/Analog transceiving unit configured to convert a transmission leakage signal generated in the coupling unit into a baseband IQ signal and generate a transmission leakage removal signal as an IQ code to cancel the transmission leakage; a leakage cancellation controller configured to receive the converted baseband IQ signal, calculate a magnitude and a phase of the signal, and output a leakage cancellation control signal; and an attenuation and amplification unit configured to attenuate a magnitude of the coupled signal, amplify an RF transmission signal output from the RF/Analog transceiving unit using a built-in power amplifier, and transmit the amplified signal to the coupling unit.

Abstract: A vector modulator of a transceiver may be provided that includes: a variable resistor having one end to which an input signal is transmitted; a variable capacitor which is connected in parallel to the variable resistor and has one end to which the input signal is transmitted; and a summing circuit which sums a signal of the other end of the variable resistor and a signal of the other of the variable capacitor.

Abstract: A vector modulator of a transceiver may be provided that includes: a variable resistor having one end to which an input signal is transmitted; a variable capacitor which is connected in parallel to the variable resistor and has one end to which the input signal is transmitted; and a summing circuit which sums a signal of the other end of the variable resistor and a signal of the other of the variable capacitor.

Abstract: The present invention is directed to reducing leakage of a transmitting signal to a receiving unit in a wireless communication system with a transmitting unit and the receiving unit sharing an antenna.

Abstract: Disclosed is a wireless communication system, more particularly, a receiver and a chipset for DSRC.

Abstract: The present invention relates to a radio frequency signal receiver, and more particularly, to a radio frequency signal receiver of a communication system, in which local devices exchange a radio frequency signal with each other. The object of the present invention is to provide a radio frequency signal receiver that exactly restores data from a received signal without a complex circuit restoring a phase of a received signal. It is another object of the present invention to provide a radio frequency signal receiver that eliminates noise when the noise is included in the received signal, estimates an exact data rate of the received signal, and exactly restores received information based on the estimated data rate thereof.

Abstract: [Problem] The present invention relates to a radio frequency signal receiver, and more particularly, to a radio frequency signal receiver of a communication system, in which local devices exchange a radio frequency signal with each other. The object of the present invention is to provide a radio frequency signal receiver that exactly restores data from a received signal without a complex circuit restoring a phase of a received signal. It is another object of the present invention to provide a radio frequency signal receiver that eliminates noise when the noise is included in the received signal, estimates an exact data rate of the received signal, and exactly restores received information based on the estimated data rate thereof.

Abstract: There is provided a dual band receiver receiving frequency signals in different bands, the receiver including: a first down converter converting a first band signal into a first intermediate frequency signal; a second down converter converting a second band signal into a second intermediate frequency signal; a first voltage control oscillator supplying a first oscillation frequency to the first down converter; a second voltage control oscillator supplying a second oscillation frequency to the second down converter; a first filter passing the first intermediate frequency signal within a desired bandwidth; a second filter passing the second intermediate frequency signal within a desired bandwidth; and a clock generator converting the first oscillation frequency of the first voltage control oscillator into sampling frequencies corresponding to integer multiples of first and second oscillation frequencies and supplying the sampling frequencies to first and second AD converters, respectively.

Abstract: A sub-harmonic frequency conversion device includes: a voltage controlled oscillator for generating first to eighth oscillation frequency (LO) signals having a constant phase difference; a first mixer for performing a switching operation to mix the first to fourth LO signals having a phase difference of 90° and input signals, and outputting first IF signals; and a second mixer for performing a switching operation to mix the fifth to eighth LO signals having a phase difference of 90° and the input signals, and outputting second IF signals. Accordingly, the sub-harmonic frequency conversion device can use the low-frequency LO signal, and the power consumption can be reduced. In addition, because the mixers are implemented using a symmetric structure of the MOS transistors, the circuit configuration can be easily implemented.