Abstract: In some embodiments, a wearable physiologic monitor comprises a mixed analog and digital application-specific integrated circuit (ASIC) including signal conditioning circuitry, an A/D converter, a real-time clock, and digital control logic. The signal conditioning circuitry includes analog amplification circuitry, analog (continuous-time or switched capacitor) filtering circuitry before the A/D converter, and in some embodiments digital (DSP) filtering circuitry after the A/D converter. The monitor includes sensors such as electrocardiogram (ECG) electrodes, accelerometers, and a temperature sensor, some of which may be integrated on the ASIC. The digital control logic receives digital physiologic data sampled at different rates, assembles the data into physiologic data packets, time-stamps at least some of the packets, and periodically stores the packets in a digital memory. The monitor may include a disposable patch including the ASIC, and a reusable, removable digital memory such as flash memory card.

Abstract: In some embodiments, a wearable physiologic monitor comprises an application-specific integrated circuit (ASIC) including signal conditioning circuitry, a real-time clock, digital control logic, and mode-selection logic for setting an operating mode of the ASIC to a stand-alone mode or a peripheral mode. In the stand-alone mode, the digital control logic periodically stores data packets including multiple sensor data types in a digital memory such as a removable flash memory card. In the peripheral mode, the data packets are transmitted to a microcontroller for processing. The monitor includes sensors such as electrocardiogram (ECG) electrodes, accelerometers, and a temperature sensor, some of which may be integrated on the ASIC. The same basic chip design may be used in the stand-alone mode in disposable patches, and in the peripheral mode in bedside devices. The operating mode may be chosen at monitor manufacture, by connecting input pins to mode-selection logic levels.