Abstract: A method for analyzing and validating clock integration properties in a circuit design is disclosed. A database of timing points that are clocked cell elements of the circuit design is generated. Next, a timing point frame showing the interaction of the clocked cell elements and the non-clocked cell elements is generated. The timing point frame graphically shows the timing network properties for the cell elements of the circuit design. A clock analysis view can be generated from the timing point frame for selected timing points. In this respect, the timing point frame shows timing points that meet a prescribed criteria (e.g., same clock domain). Therefore, the clock analysis view provides a graphical representation of timing and clock interactions for the circuit design.

Abstract: A method for analyzing and validating clock integration properties in a circuit design is disclosed. A database of timing points that are clocked cell elements of the circuit design is generated. Next, a timing point frame showing the interaction of the clocked cell elements and the non-clocked cell elements is generated. The timing point frame graphically shows the timing network properties for the cell elements of the circuit design. A clock analysis view can be generated from the timing point frame for selected timing points. In this respect, the timing point frame shows timing points that meet a prescribed criteria (e.g., same clock domain). Therefore, the clock analysis view provides a graphical representation of timing and clock interactions for the circuit design.