Abstract: A memory device includes a memory cell array, an internal logic circuit having a first set of data paths, a second set of data paths, a multiplexer circuit, a storage circuit, and a decoder. The memory cell array is used for storing data. The multiplexer circuit is disposed between the first set of data paths and the second set of data paths. The storage circuit is used for storing g fault information associated with the first set of data paths. The decoder is used for reading and decoding the fault information and for controlling the multiplexer circuit to select a neighboring non-faulty data path to form a connection with a data path based on the fault information if a specific data path is faulty, so as to form a funnel-like shape connection structure.

Abstract: A stacked memory device includes a first memory die and a second memory die. The first memory die has multi-layer structure and each of a plurality of layers of the first memory die includes at least a memory cell region and a through-silicon-via (TSV) region. The first memory die is electrically connected to an integrated circuit device through a plurality of vertical interconnects within the TSV region. The second memory die is disposed between the first memory die and the integrated circuit device. The second memory die has single layer structure, and the second memory die includes at least a memory cell region and a TSV region. The second memory die is electrically connected to the integrated circuit device through surface bonding.

Abstract: An apparatus for page-copy data accessing is provided, which includes a memory cell array, bit-line sense-amplifier/buffers (BLSABFs), page buffers and a logic operation processing circuit. Data voltage signals on bit-lines in a memory section are transferred to the bit-lines in an adjacent memory section adjacent to the memory section by BLSABFs and the voltage data signals are sequentially propagated across subsequent memory sections through BLSABFs between the subsequent memory sections. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising target location to write voltages to the memory cells at the target location. The page buffers are configured to receive data voltage signals from the coupled BLSABFs to a data interface.

Abstract: A method for handling defective regular local wordlines in a memory module is provided. The method includes: providing one or more sets of spare local wordlines; utilizing a spare control logic to generate a plurality of match signals by comparing an input address with a plurality of fail addresses; utilizing the spare control logic to generate at least one assignable bit according to the plurality of match signals; utilizing a local wordline pre-decoder to generate a local wordline activation signal according to one of at least one bit of the input address and the at least one assignable bit; and in accordance with the input address and the local wordline activation signal, utilizing the one or more spare wordline decoders to activate one spare local wordline from the one or more sets of spare local wordlines for repairing/replacing a defective regular local wordline.

Abstract: A method for handling defective regular local wordlines in a memory module is provided. The method includes: providing one or more sets of spare local wordlines; utilizing a spare control logic to generate a plurality of match signals by comparing an input address with a plurality of fail addresses; utilizing the spare control logic to generate at least one assignable bit according to the plurality of match signals; utilizing a local wordline pre-decoder to generate a local wordline activation signal according to one of at least one bit of the input address and the at least one assignable bit; and in accordance with the input address and the local wordline activation signal, utilizing the one or more spare wordline decoders to activate one spare local wordline from the one or more sets of spare local wordlines for repairing/replacing a defective regular local wordline.

Abstract: A timing control circuit for use in a memory module includes: a clock generation circuit and a data queue. The clock generation circuit is configured to generate one or more delayed versions of an external clock signal and select one of the external clock signal and the one or more delayed versions of the external clock signal to generate a tracking clock signal according to a write latency count satisfaction indication signal and a row-to-column delay end indication signal. The data queue is configured to queue input data according to the external clock signal and generate an output data signal by de-queuing the queue data according to the tracking clock signal. Specifically, the output data signal and the tracking clock signal are utilized to perform a write operation within the memory module in response to an external write command.

Abstract: A memory device is provided, which includes a memory array and data transfer circuits. The memory array is divided into a plurality of memory sections, and each memory section includes memory cells. Each data transfer circuit is disposed between two memory sections. A data movement occurring from all or a selected set of bit-lines or bit-line pairs between any two adjacent memory sections of the memory array is performed or to data interfaces other than the bit-lines or bit-line pairs. Data signals of all or the selected set of bit-lines or bit-line pairs of two adjacent memory sections are sensed, latched, buffered and repeated during the data movement by a data transfer circuit and data movement is sequentially performed between two memory sections to facilitate the transfer of data signals to any memory section of the memory array without the need for global or trans-multiple-section data lines.

Abstract: An apparatus for page-copy data accessing is provided, which includes a memory cell array, bit-line sense-amplifier/buffers (BLSABFs), page buffers and a logic operation processing circuit. Data voltage signals on bit-lines in a memory section are transferred to the bit-lines in an adjacent memory section adjacent to the memory section by BLSABFs and the voltage data signals are sequentially propagated across subsequent memory sections through BLSABFs between the subsequent memory sections. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising target location to write voltages to the memory cells at the target location. The page buffers are configured to receive data voltage signals from the coupled BLSABFs to a data interface.

Abstract: Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.

Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.

Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.

Abstract: An one-time programmable memory cell includes: an upper electrode; an insulating layer beneath the upper electrode; and a lower electrode with electrical field enhancement structure beneath the insulating layer, wherein the electrical field enhancement structure has a least one tip portion. The one-time programmable memory cell also includes a shallow trench isolation region, disposed adjacent to the insulating layer and the lower electrode, wherein the electrical field enhancement structure is surrounded by the shallow trench isolation region and the upper electrode partially covers the shallow trench isolation region.

Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.

Abstract: Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.

Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.

Abstract: An apparatus for enhancing prefetch access in a memory module may include a memory chip. The memory chip includes a memory cell array, a plurality of bit lines and a plurality of word lines, a plurality of BLSAs, and a plurality of main data lines. The memory cell array may be arranged to store data, and the plurality of bit lines and the plurality of word lines may be arranged to perform access control of the memory cell array. The plurality of BLSAs may sense a plurality of bit-line signals restored from the plurality of memory cells and convert the plurality of bit-line signals into a plurality of amplified signals, respectively. The main data lines may directly output the amplified signals, through selection of CSLs of the BLSAs on the memory chip, to a secondary semiconductor chip, for performing further processing of the memory module, thereby enhancing the prefetch access.

Abstract: A method for testing a semiconductor die is provided. The method includes the following steps: charging a die pad of the semiconductor die to a precharge level; stopping charging the die pad to detect a period of time required for a voltage level of the die pad to change from the precharge level to a reference level, and accordingly generating a detection result; and determining a leakage current of the die pad according to the detection result.

Abstract: A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.

Abstract: A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.

Abstract: A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.