Abstract: A programmable logic unit circuit comprising a data memory circuit, a combinational logic circuit supplied with at least two input signals, two input select circuits for, based on the stored data in the data memory circuit, selecting the two input signals supplied to the combinational logic circuit from more than two input signals, a clock-synchronized circuit for supplying the output signal from the combinational logic circuit in synchronization with a clock signal, and a 3-state-output type output select circuit for selecting either the output signal of the combinational logic circuit or the output signal of the clock-synchronized circuit, depending on the stored data in the data memory circuit.