Patents Assigned to Pixel Velocity, Inc.
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Patent number: 8587661Abstract: According to one embodiment, a controller for a surveillance system includes ports for coupling a camera, synchronization logic blocks coupled to the ports, an information aggregation logic block coupled to the camera ports, and an output port coupled to the information aggregation logic block. According to another embodiment, a method of scaling a surveillance system includes synchronizing a plurality of cameras, capturing images from the synchronized cameras, aggregating at least two processed synchronized images, and processing the aggregated synchronized images.Type: GrantFiled: February 21, 2008Date of Patent: November 19, 2013Assignee: Pixel Velocity, Inc.Inventor: David L. McCubbrey
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Patent number: 8230374Abstract: A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.Type: GrantFiled: December 14, 2007Date of Patent: July 24, 2012Assignee: Pixel Velocity, Inc.Inventor: David L. McCubbrey
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Patent number: 8019118Abstract: One of the embodiments of the invention includes a method of identifying illegal uses of copyright material. The steps of the method preferably include the steps of: (a) providing a primary digital media object, (b) associating an auxiliary construct with the object, (c) transforming the construct using at least one of the attributes of the object to generate a unique key representative of the primary object, (d) receiving a plurality of secondary digital media objects, (e) performing steps (b) and (c) on the secondary objects to generate unique keys representative of the secondary objects, (f) comparing the keys of the secondary objects with the key of the primary object to identify if any of the secondary objects are substantially similar to the primary object.Type: GrantFiled: May 18, 2010Date of Patent: September 13, 2011Assignee: Pixel Velocity, Inc.Inventors: Stanley Sternberg, William Dargel, John W. Lennington, Thomas Voiles
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Patent number: 7756291Abstract: One of the embodiments of the invention includes a method of identifying illegal uses of copyright material. The steps of the method preferably include the steps of: (a) providing a primary digital media object, (b) associating an auxiliary construct with the object, (c) transforming the construct using at least one of the attributes of the object to generate a unique key representative of the primary object, (d) receiving a plurality of secondary digital media objects, (e) performing steps (b) and (c) on the secondary objects to generate unique keys representative of the secondary objects, (f) comparing the keys of the secondary objects with the key of the primary object to identify if any of the secondary objects are substantially similar to the primary object.Type: GrantFiled: December 9, 2008Date of Patent: July 13, 2010Assignee: Pixel Velocity, Inc.Inventors: John W. Lennington, Thomas Voiles, Stanley Sternberg, William Dargel
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Patent number: 7587699Abstract: An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O.Type: GrantFiled: May 10, 2006Date of Patent: September 8, 2009Assignee: Pixel Velocity, Inc.Inventor: David L. McCubbrey
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Patent number: 7474759Abstract: Physical objects, including still and moving images, sound/audio and text are transformed into more compact forms for identification and other purposes using a method unrelated to existing image-matching systems which rely on feature extraction. An auxiliary construct, preferably a warp grid, is associated with an object, and a series of transformations are imposed to generate a unique visual key for identification, comparisons, and other operations. Search methods are also disclosed for matching an unknown image to one previously represented in a visual key database. Broadly, a preferred search method sequentially examines candidate database images for their closeness of match in a sequential order determined by their a priori match probability. Thus, the most likely match candidate is examined first, the next most likely second, and so forth.Type: GrantFiled: November 13, 2001Date of Patent: January 6, 2009Assignee: Pixel Velocity, Inc.Inventors: Stanley Sternberg, William Dargel, John W Lennington, Thomas Voiles
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Patent number: 7451410Abstract: The stackable motherboard 10 of the first embodiment includes: a circuit board 19 having a first side 14 and a second side 17 opposite the first side 14, a processor 16 mounted on the circuit board 19, a first peripheral interconnect 18, and a second peripheral interconnect 90. The stackable motherboard 10 also preferably includes: a first motherboard interconnect 99 mounted on the first side 14 of the circuit board 19 and adapted to communicate data between the processor 16 and a first auxiliary motherboard, and a second motherboard interconnect 94 mounted on the second side 17 of the circuit board 19 and adapted to communicate data between the processor 16 and a second auxiliary motherboard.Type: GrantFiled: November 26, 2004Date of Patent: November 11, 2008Assignee: Pixel Velocity Inc.Inventor: David L. McCubbrey
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Patent number: 7073158Abstract: An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components.Type: GrantFiled: May 19, 2003Date of Patent: July 4, 2006Assignee: Pixel Velocity, Inc.Inventor: David L. McCubbrey