Patents Assigned to Pixel Velocity, Inc.
  • Patent number: 8587661
    Abstract: According to one embodiment, a controller for a surveillance system includes ports for coupling a camera, synchronization logic blocks coupled to the ports, an information aggregation logic block coupled to the camera ports, and an output port coupled to the information aggregation logic block. According to another embodiment, a method of scaling a surveillance system includes synchronizing a plurality of cameras, capturing images from the synchronized cameras, aggregating at least two processed synchronized images, and processing the aggregated synchronized images.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: November 19, 2013
    Assignee: Pixel Velocity, Inc.
    Inventor: David L. McCubbrey
  • Patent number: 8230374
    Abstract: A method of partitioning an algorithm between hardware and software includes accepting a user defined algorithm specified in a source code, identifying worker methods and feature extraction methods within the user defined algorithm, replacing worker methods in the source code with hardware logic, replacing feature extraction methods with a combination of hardware logic and software libraries that interface with the hardware logic, and outputting an FPGA programming specification of the hardware logic and interface libraries.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: July 24, 2012
    Assignee: Pixel Velocity, Inc.
    Inventor: David L. McCubbrey
  • Patent number: 8019118
    Abstract: One of the embodiments of the invention includes a method of identifying illegal uses of copyright material. The steps of the method preferably include the steps of: (a) providing a primary digital media object, (b) associating an auxiliary construct with the object, (c) transforming the construct using at least one of the attributes of the object to generate a unique key representative of the primary object, (d) receiving a plurality of secondary digital media objects, (e) performing steps (b) and (c) on the secondary objects to generate unique keys representative of the secondary objects, (f) comparing the keys of the secondary objects with the key of the primary object to identify if any of the secondary objects are substantially similar to the primary object.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: September 13, 2011
    Assignee: Pixel Velocity, Inc.
    Inventors: Stanley Sternberg, William Dargel, John W. Lennington, Thomas Voiles
  • Patent number: 7756291
    Abstract: One of the embodiments of the invention includes a method of identifying illegal uses of copyright material. The steps of the method preferably include the steps of: (a) providing a primary digital media object, (b) associating an auxiliary construct with the object, (c) transforming the construct using at least one of the attributes of the object to generate a unique key representative of the primary object, (d) receiving a plurality of secondary digital media objects, (e) performing steps (b) and (c) on the secondary objects to generate unique keys representative of the secondary objects, (f) comparing the keys of the secondary objects with the key of the primary object to identify if any of the secondary objects are substantially similar to the primary object.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: July 13, 2010
    Assignee: Pixel Velocity, Inc.
    Inventors: John W. Lennington, Thomas Voiles, Stanley Sternberg, William Dargel
  • Patent number: 7587699
    Abstract: An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. The mapper module utilizes the output from the analyzer module and determines where the required logic components must be placed on a given target FPGA in order to reliably route, without interference, the required interconnections between various components and I/O.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: September 8, 2009
    Assignee: Pixel Velocity, Inc.
    Inventor: David L. McCubbrey
  • Patent number: 7474759
    Abstract: Physical objects, including still and moving images, sound/audio and text are transformed into more compact forms for identification and other purposes using a method unrelated to existing image-matching systems which rely on feature extraction. An auxiliary construct, preferably a warp grid, is associated with an object, and a series of transformations are imposed to generate a unique visual key for identification, comparisons, and other operations. Search methods are also disclosed for matching an unknown image to one previously represented in a visual key database. Broadly, a preferred search method sequentially examines candidate database images for their closeness of match in a sequential order determined by their a priori match probability. Thus, the most likely match candidate is examined first, the next most likely second, and so forth.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: January 6, 2009
    Assignee: Pixel Velocity, Inc.
    Inventors: Stanley Sternberg, William Dargel, John W Lennington, Thomas Voiles
  • Patent number: 7451410
    Abstract: The stackable motherboard 10 of the first embodiment includes: a circuit board 19 having a first side 14 and a second side 17 opposite the first side 14, a processor 16 mounted on the circuit board 19, a first peripheral interconnect 18, and a second peripheral interconnect 90. The stackable motherboard 10 also preferably includes: a first motherboard interconnect 99 mounted on the first side 14 of the circuit board 19 and adapted to communicate data between the processor 16 and a first auxiliary motherboard, and a second motherboard interconnect 94 mounted on the second side 17 of the circuit board 19 and adapted to communicate data between the processor 16 and a second auxiliary motherboard.
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: November 11, 2008
    Assignee: Pixel Velocity Inc.
    Inventor: David L. McCubbrey
  • Patent number: 7073158
    Abstract: An automated system and method for programming field programmable gate arrays (FPGAs) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed up the process of implementing and testing a fully written high-level user-defined algorithm to a matter of a few minutes, rather than the days, weeks or even months presently required using conventional software tools. The automated system includes an analyzer module and a mapper module. The analyzer determines what logic components are required and their interrelationships, and observes the relative timing between the required components and their partial products. It also ascertains when signal delays are required between selected components.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: July 4, 2006
    Assignee: Pixel Velocity, Inc.
    Inventor: David L. McCubbrey