Patents Assigned to Pixelplus Co., Ltd.
  • Patent number: 7929212
    Abstract: There is provided an image sensor having micro lenses of which pitches decrease by different ratios according to left side and right side ratios, which are arranged in different ratios according to upper side and right side ratios, and of which pitches in the edge area are equal to a pixel pitch to arrange the micro lenses in a predetermined interval, thereby capable of preventing ambient sensitivity from deteriorating and suppressing crosstalk.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: April 19, 2011
    Assignee: Pixelplus Co., Ltd.
    Inventors: Dae Sung Min, Jung Soon Shin
  • Patent number: 6933974
    Abstract: A CMOS image sensor that outputs signal data before outputs reset data, and a driving method therefor. The CMOS image sensor includes a pixel sensor, a data I/O line, a double sampling circuit and an output circuit. The pixel sensor generates signal data and reset data. The signal data has a voltage level depending on an amount of photo-charge produced in response to energy received externally. The reset data is produced in a reset mode. The data I/O line transfers the generated signal data and the reset data. The double sampling circuit samples the signal data and then the reset data, from the data I/O line, and drives an output terminal. The output circuit outputs data related to a voltage level of the output terminal.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: August 23, 2005
    Assignee: Pixelplus Co., Ltd.
    Inventor: Seo Kyu Lee
  • Patent number: 6528833
    Abstract: A CMOS active pixel of increased sensitivity includes a floating diffusion layer, a photo-diode, a reset circuit and an output circuit The floating diffusion layer is of a first dopant type and receives a signal charge. The photo-diode generates the signal charge depending on an energy inputted thereto and transfers the signal charge to the floating diffusion layer. The photo-diode has first and second lower diode dopant layers of the first dopant type and an upper diode dopant layer of a second dopant type. The polarity of the second dopant type is opposite to that of the first dopant type. The first and second lower diode dopant layers are formed to contact a lower portion of the upper diode dopant layer. The upper diode dopant layer and the first lower diode dopant layer are formed to contact the floating diffusion layer. The second lower diode dopant layer is formed to contact the first lower diode dopant layer.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: March 4, 2003
    Assignee: Pixelplus Co., Ltd.
    Inventors: Seo Kyu Lee, Dae Sung Min