Abstract: The invention is a circuit and method for automatically adjusting the phase and frequency of a pixel clock derived from analog image data. The circuit includes a phase locked loop circuit adapted to generate a phase locked loop clock responsive to a reference signal and an edge detector circuit adapted to generate an edge pulse signal corresponding to a transition of an analog data signal. A phase detector circuit is adapted to identify a phase of the phase locked loop clock associated to the transition of the analog data and thereby generate a phase adjust signal. A phase adjust circuit is adapted to generate a pixel clock by adjusting the phase of the phase locked loop clock responsive to the phase adjust signal.

Abstract: An output pixel datum is produced from input pixel data by a method wherein the brightness levels of several input pixels closely associated coordinate-wise with the output pixel, are examined to determine whether a relatively less complex graphics-optimized scaling procedure, or a relatively more sophisticated video-optimized scaling procedure, should be carried out. In the second case, directional interpolation is performed with a plurality of directions, e.g., being considered to determine the direction of minimum brightness level gradient. A plurality of intermediate pixels, e.g., four, are produced, which are aligned perpendicularly to the minimum brightness level gradient direction, their brightness levels being determined from relevant input pixels using linear interpolation. The output pixel brightness level is determined from the intermediate pixels through the use of an appropriate filtering technique, e.g., polyphase FIR filtering.

Abstract: The invention is a method and apparatus for reducing noise in an image. The method and apparatus involves calculating a plurality of directional operators, comparing the directional operators to a predetermined threshold, and applying a filter responsive to the comparing. The method and apparatus computes the directional operators by taking a weighted sum of the absolute differences between a target pixel and its surrounding pixels. The comparison signals to the method or apparatus the existence of a line or edge. If the method or apparatus detects no edge or line, the method applies a smoothing or averaging filter. If the method or apparatus detects an edge or line, the method applies a median filter in the direction with a minimum directional difference.

Abstract: The present invention provides an apparatus and method for an adaptive Y/C separator that selects between input filters responsive to features of video signals. The adaptive Y/C separator can monitor the results of numerous filters and choose a combination of separators dependent upon signal properties. The adaptive Y/C separator can even blend results of the Y/C separators to improve signal quality.

Abstract: A method and system for performing fuzzy logic based de-interlacing on film source fields that might be mixed with video on film. An embodiment of the invention comprises an adaptive de-interlacer by weighing between merge operation and interpolation operation in the case of occurring video on film motion object. A weighing factor is generated from video on film pattern based on fuzzy logic inference rules. This weighing factor specifies the weighting between merging and interpolating in assigning the pixel values of the progressive display output.

Abstract: A projector determines horizontal and vertical tilt angles. Using the tilt angles and the inherent properties of the projector, keystone correction corner points for the image can be computed. The keystone correction corner points can be used to perform keystone correction on the image.

Abstract: An output pixel datum is produced from input pixel data by a method wherein the brightness levels of several input pixels closely associated coordinate-wise with the output pixel, are examined to determine whether a relatively less complex graphics-optimized scaling procedure, or a relatively more sophisticated video-optimized scaling procedure, should be carried out. In the second case, directional interpolation is performed with a plurality of directions, e.g., being considered to determine the direction of minimum brightness level gradient. A plurality of intermediate pixels, e.g., four, are produced, which are aligned perpendicularly to the minimum brightness level gradient direction, their brightness levels being determined from relevant input pixels using linear interpolation. The output pixel brightness level is determined from the intermediate pixels through the use of an appropriate filtering technique, e.g., polyphase FIR filtering.

Abstract: We describe and claim a delay locked loop harmonic detector and associated method. A delay locked loop includes a detection circuit to generate a detection signal responsive to an input clock and a control circuit to synchronize the delay locked loop to a fundamental of the input clock responsive to the detection signal. A method includes detecting harmonic synchronization in a delay locked loop responsive to an input clock and locking the delay locked loop to a fundamental of the input clock responsive to the detecting.

Abstract: The invention provides a system and method for mixing graphics and text in an on-screen display application. The system includes font and character memories. The font memory stores bitmaps associated with characters to be displayed on a display device. The character memory, in turn, includes a font portion and an attribute portion. The font portion stores a font index of characters to be displayed, the font index being used to address the font memory. The attribute portion stores a plurality of attributes associated with a character to be displayed. The plurality of attributes includes a text/graphic attribute indicative of a text character or a graphic clip and a redirection attribute indicating mapping of a main color memory using an expanded color memory.

Abstract: The invention relates to a system and method for visually displaying data and, more particularly, to a system and method for displaying full screen high frequency data on a flat panel without using a frame buffer that would otherwise not be displayed. The system and method displays a full screen, color, image that allows a user to adjust its computer back to a correct setting. That is, to exit the high frequency mode that produced the high frequency digital data in the first instance without having to connect a CRT, reboot, or the like. The system and method drives the panel's rows and columns so as to display interlaced data, thereby reducing the effective vertical frequency of the data. Because the human eye is incapable of perceiving the blank lines, the screen appears complete just as it does in the normal mode.

Abstract: We describe a weighted absolute difference based deinterlace method and apparatus. The deinterlace method and apparatus uses weighted absolute differences along different directions as means for interpolating pixel data using edge orientation detection. The apparatus includes a memory adapted to store a current and previous fields and predetermined portions of a future field of an input signal. A motion detector is adapted to detect motion between the future and previous fields. An interpolating circuit is adapted to generate a plurality of output pixels using a corresponding plurality of methodologies. And a switch is adapted to select between the plurality of output pixels responsive to the motion detector.

Abstract: The invention is a method and apparatus for reducing noise in an image. The method and apparatus involves calculating a plurality of directional operators, comparing the directional operators to a predetermined threshold, and applying a filter responsive to the comparing. The method and apparatus computes the directional operators by taking a weighted sum of the absolute differences between a target pixel and its surrounding pixels. The comparison signals to the method or apparatus the existence of a line or edge. If the method or apparatus detects no edge or line, the method applies a smoothing or averaging filter. If the method or apparatus detects an edge or line, the method applies a median filter in the direction with a minimum directional difference.

Abstract: The invention relates to a synchronization signal decoder and associated method for improving digital image display. A composite video stream includes a distortion compliant signal and a synchronization signal. A level shift circuit is adapted to shift a voltage level of the composite video stream such that the distortion compliant signal is readily distinguishable from the synchronization signal. A level shift disable circuit is adapted to disable the level shift circuit responsive to the composite video stream.

Abstract: The present invention provides an ADC apparatus and method for improving effective bit resolution and suppressing digital reconstruction artifacts with an anti-aliasing filter and an over-sampled input. ADC resolution can be increased by combining a dither signal with a sampled signal and then after digitization, filtering out the dithered signal. Designing a notch in the filter corresponding to the attenuation frequency attenuates residual effects.

Abstract: A CMOS output cell with multiple output modes is disclosed. In one embodiment, the cell drives a differential output signal on two output pads in one mode and two single-ended output signals on the two output pads in another mode. Differential and single-ended driver transistors are included for this purpose. A logic circuit disables unused driver transistors, and supplies appropriate drive signals to those transistors for each mode. When disabled, the driver transistors serve an electrostatic discharge (ESD) protection function, at least partially alleviating the need for ESD-specific devices in the cell. The diminished need for ESD-specific devices allows the cell to offer a highly flexible chip interface, with little or no increase in circuit area over a conventional cell that offers only single-ended or differential output.

Abstract: An improved receiver architecture is disclosed comprising a latching mechanism coupled to receive a data stream, and a signal generator for generating latching control signals for controlling the operation of the latching mechanism. The signal generator generates one latching control signal per data period of the data stream, with each latching control signal coinciding approximately with the midpoint of a corresponding data period. The signal generator generates the latching control signals based upon a reference signal, which in one embodiment, coincides approximately with the midpoint of a data period of the data stream. The receiver may further comprise an adjustable delay element and a delay adjustment control. The adjustable delay element receives a clock signal and imposes a variable delay thereon to derive the reference signal used to generate the latching control signals. The magnitude of the variable delay is controlled by the delay adjustment control.

Abstract: The invention describes a system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input vertical refresh rate and displays the image data at a vertical refresh rate that is a predetermined fraction of the input vertical refresh rate.

Abstract: A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

Abstract: A projector determines horizontal and vertical tilt angles. Using the tilt angles and the inherent properties of the projector, keystone correction corner points for the image can be computed. The keystone correction corner points can be used to perform keystone correction on the image.

Abstract: An image processing circuit includes a processor that receives an encoded portion of a first version of an image. The processor decodes this encoded portion directly into a decoded portion of a second version of the image, the second version having a resolution that is different than the resolution of the first version. Therefore, such an image processing circuit can decode an encoded hi-res version of an image directly into a decoded lo-res version of the image. Alternatively, the image processing circuit includes a processor that modifies a motion vector associated with a portion of a first version of a first image. The processor then identifies a portion of a second image to which the modified motion vector points, the second image having a different resolution than the first version of the first image.