Abstract: The digital switching module (DSM) is arranged as an LSI device providing digital (p.c.m.) switching for 256 channels in a space-time-space format. It is unidirectional in operation and is capable of switching data (digitally encoded speech) from any incoming channel to any outgoing channel. It is arranged to act as a building block in constructing larger digital switching networks. The DSM can be programmed to permit combinations of parallel or serial operation at input and output data interfaces, the mode being selected by the length of the pulse width of the frame start reference signal. The switching configuration of input channels to output channels is held within the DSM and can be amended by messages sent along a serial control interface. Interrogation of the switching state and of the data passing through the switch is provided by messages applied to an output control interface. The DSM can be arranged into square arrays to provide full availability switching for a greater number of channels.
Type:
Grant
Filed:
June 23, 1981
Date of Patent:
January 10, 1984
Assignee:
The Plessey Company plc
Inventors:
Joseph A. French, Thomas S. Maddern, Alexander S. Philip
Abstract: It has been proposed to base advanced Digital Switching networks on a modular array using Digital Switch Modules (DSM). It has been found, for large traffic handling Digital switching systems, that the cross-office delay encountered in multi-stage networks based on 8.times.8 Digital Switching Modules (DSM's) is unacceptably large. To maintain the flexibility provided by the multi-stage concepts a demultiplexing/mixing/remultiplexing stage (DMR) is introduced to replace intermediate DSM ranks. The DMR is used to provide a preset time/space switching function within the total trunking providing the availability of a controlled stage but without the control and delay penalties associated with a fully flexible DSM or the control and link blocking disadvantages associated with a pure space switch. The DMR effectively acts as a pre-programmed or counter driven DSM.
Abstract: In modern digital telecommunications switching networks the switch block may be a duplicated plane time-space-time arrangement in which each time switch stage and each space switch stage is controlled by control stores. Each control store is cross-office slot ordered and is arranged to be loaded by the central control with the identity of the connection required for the relevant cross-office slot. At each busy cross-office slot in a time switch control store a 12 bit address word is retrieved. Ten bits are used to define the connection while the two remaining bits act as a busy bit and a parity bit. Each space switch control store contains in cross-office slot order eight bit address words (6 bits address plus busy and parity bits). The busy bits are used when interrogating the trunking for free paths and they are also used to control the application of idle codes to free slots in the speech path. The parity bits within the control stores are used to initiate pattern insertion on the speech highways.
Type:
Grant
Filed:
August 7, 1980
Date of Patent:
July 12, 1983
Assignees:
The Plessey Company plc, The Plessey Company plc
Abstract: In digital telecommunication switching systems the switch block includes an alarm monitor unit (AMU) which is used for initiating maintenance related commands in addition to monitoring, persistance checking and filtering alarm outputs. It is particularly useful in relieving the main processing system of routine alarm processing. The AMU collects line and switch block fault indicators from the digital line termination units DLT, applies persistance checks to determine if the alarm is transient or significant and depending on the outcome it identifies the precise location of the alarm and formats an error report to the processor. Each DLT communicates to and from an AMU by way of an alarm interface unit in the time switch serving the DLT using status and command highways respectively over 2048 kb/s balanced lines. The DLT uses 32 time slots to code-up status information in a time related manner (i.e. bit n of 256 has a defined significance such as speech parity error plane 1, channel m).
Abstract: It is an emerging international telecommunications requirement that all 32 channels of the p.c.m. multiplex must be switchable. The switching of channel zero relates to the "spare bits" not defined for synchronization purposes and these bits may be used as a data-bearer for network administration or control purposes. Digital telecommunication switching network, therefore, must be capable of concentrating channel assemblies of these spare bits into one transmit multiplex which may be connected to a spare bit data processor remote from the switching network or co-located with it.
Type:
Grant
Filed:
August 6, 1980
Date of Patent:
December 21, 1982
Assignee:
The Plessey Company plc
Inventors:
Geoffrey Chopping, Robert V. Moberly, Alexander S. Philip