Patents Assigned to Plessey Electronics Systems Corp.
  • Patent number: 4998079
    Abstract: A coupler for a balanced two wire data transmission line includes input and output ports as well as a forward coupled port and a reflected coupled port. The coupler is constructed of passive components including transformers and resistors to provide at the forward coupled port a signal proportional to the signal transmitted from a source to a load and provide at the reflected coupled port a signal proportional to the magnitude of the signal reflected from the load due to mismatch.
    Type: Grant
    Filed: January 16, 1990
    Date of Patent: March 5, 1991
    Assignee: Plessey Electronic Systems Corp.
    Inventor: C. Earle Theall, Jr.
  • Patent number: 4996630
    Abstract: A Very Large Hybrid Module (VLHM) for packaging electronic components provides a hermetic enclosure formed by a hermetic substrate on which the components are mounted together with a hermetic lid surrounding groups of the components. A second substrate outside the hermetic enclosure is utilized for providing connections between the electronic components.
    Type: Grant
    Filed: September 27, 1989
    Date of Patent: February 26, 1991
    Assignee: Plessey Electronic Systems Corp.
    Inventors: Ralph Liguori, Kurt R. Goldhammer, Lothar Laermer
  • Patent number: 4965810
    Abstract: Digital circuits increase reliability of a decoder for differential phase-shift keyed signals. A tapped delay line delays the input signal by a variable amount, substantially equal to one bit time of the modulated data, and provides the delayed signal to a multiplier for generating a product signal. In response to changes in frequency of the input signal, a control system selects different taps of the delay line to provide the delayed signal for multiplication by the modulated input signal. The control signal includes a feedback loop, wherein a phase difference between the signal at the selected tap and the input signal is used to change a count in an up/down counter. A tap selecting multiplexer provides an output from specified taps in response to particular values of the count.
    Type: Grant
    Filed: November 17, 1988
    Date of Patent: October 23, 1990
    Assignee: Plessey Electronics Systems Corp.
    Inventors: Mark L. Peischl, Relan N. Vinluan
  • Patent number: 4963945
    Abstract: A band rejection filtering arrangement utilizing bandpass filters each terminated by a matched load. A quadrature hybrid circuit divides the input signals and applies them to the bandpass filters. Signals within the rejection band are dissipated by the filters and matched loads, whereas desired signals are reflected. The reflected signals are then combined by the quadrature hybrid circuit to provide the band rejected output. This arrangement is made switchable between an all pass mode and the band rejection mode by providing PIN diodes between the quadrature hybrid circuit and the bandpass filters.
    Type: Grant
    Filed: April 7, 1989
    Date of Patent: October 16, 1990
    Assignee: Plessey Electronic Systems Corp.
    Inventors: David M. Cooper, Gerald Lebleboojian
  • Patent number: 4964028
    Abstract: A voltage converting power supply having current limiting characteristics wherein a flyback converter is operated in a load dependent half-wave mode. Constant pulse width switching at a variable rate is utilized for regulation and, by setting the maximum switching frequency, current limiting is achieved.
    Type: Grant
    Filed: October 26, 1989
    Date of Patent: October 16, 1990
    Assignee: Plessey Electronic Systems Corp.
    Inventor: Vincent J. Spataro
  • Patent number: 4937845
    Abstract: An N stage Gray code generator includes an N stage binary counter having an input for receiving clock pulses to be counted and providing N outputs forming an N bit binary code. N minus 1 storage stages capable of being toggled between a logic "1" and a logic "0" state, each having a toggle input to cause them to toggle, have their toggle inputs coupled to the outputs of the first N minus 1 stages of the binary counter. The outputs of the N minus 1 storage stages form the first N minus 1 Gray code outputs and the most significant output of the binary counter provides the most significant output of the Gray code generator.
    Type: Grant
    Filed: August 1, 1988
    Date of Patent: June 26, 1990
    Assignee: Plessey Electronic Systems Corp.
    Inventor: Richard C. Warner
  • Patent number: 4897620
    Abstract: A continuous phase shift modulation system wherein, for each of the in-phase and quadrature components, adjacent half-cosine pulses of the same polarity are joined by a continuous transition modulation signal which maintains continuity of the waveform and at least its first derivative. When this occurs, the other component signal is adjusted to maintain constant the vector sum of the component signals.
    Type: Grant
    Filed: March 6, 1989
    Date of Patent: January 30, 1990
    Assignee: Plessey Electronic Systems Corp.
    Inventor: Ronald Y. Paradise
  • Patent number: 4881800
    Abstract: To stabilize the line-of-sight of an optical image relative to a commanded line-of-sight, a stabilization system consisting of a mirror having two limited degrees of freedom, a two axis gyroscope having its two sensitive axes perpendicular to the LOS, a pickoff sensor feeding back mirror angular position, servo compensators that provide mirror torque commands to a two axis mirror torquer, and the electronic hardware that ties these components together is used.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: November 21, 1989
    Assignee: Plessey Electronic Systems Corp.
    Inventors: Charles R. Fuchs, David A. Haessig, Jr., David L. Heckathorn, Jordan S. Kass, Peter Lindsay, Joseph J. Volpe