Abstract: A programmable logic device having a plurality of functional units, a programmable interconnect matrix for connecting the functional units together, input and output pins coupled to the interconnect matrix, and programmable inverters connected between the pins and conductive lines of the matrix to permit external signals leading into or out of the interconnect matrix to be inverted, if desired. Each functional unit may itself be a programmable logic device with inputs, an AND array connected to the inputs, an OR array connected to the AND array, optional registers and inverters on the output side of the OR array, and outputs coupled to the OR array, the registers or the inverters. The programmable interconnect matrix includes two sets of conductive lines crossing one another and connectable by programmable links at each intersection. The lines connect to functional unit inputs and to input and output pins.

Abstract: A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit. Output pins connect directly to outputs of functional units. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by EPROM, or EEPROM switches.

Abstract: Apparatus for programming an OR gate, an AND gate or an EXCLUSIVE-OR gate to accept or not accept an input signal at an input terminal of the gate. The apparatus includes two pass transistors, a source of high or low voltage depending on the gate to be programmed, and a control signal that is used for programming the gates of the pass transistors. The two pass transistors may be of the same channel type i.e.,. both n-channel or both p-channel, or they may be of opposite channel types. This apparatus provides positive input signals from a group of input signals to avoid voltage signal ambiguities in programming the gates. Use of these programmable gates in combination in an AND-OR array is illustrated.

Abstract: A programmable logic device that provides an AND gate array connected to an OR gate array connected to a third logic level, a logic expander module. The module provides programmable selection of any of 16 one- and two-variable logic functiosn or any of 256 one-, two- and three-variable logic functions. In one embodiment, the invention uses logic function gates such as AND, OR, XOR and inverter gates to form the logic functions. In a second embodiment and a third embodiment, a look-up table and an array of pass transistors, respectively, are used to form the logic functions.

Abstract: A configuration control circuit in an integrated circuit device, such as a programmable logic device, having a programmable memory for storing configuration bits and one or more shift registers which are loadable from the memory. The memory is an array of nonvolatile memory cells that can be user programmed with data corresponding to a desired device architecture. The shift registers are loaded with this data upon power up or a reset. The registers in combination with other circuit gates control the operation of the device such that a particular architecture is implemented. The various configurations can be tested without altering the contents of the memory by loading the shift register externally.