Patents Assigned to PMC-Sierra Limited
  • Patent number: 6633865
    Abstract: An apparatus for executing a multiple step database lookup procedure, the apparatus including a plurality of processing units, at least two processing units being coupled to a memory containing a database to be looked up, and a plurality of data pipelines which couple the plurality of processing units to each other and to external apparatus, wherein each processing unit executes at least one step in the multiple step database lookup procedure.
    Type: Grant
    Filed: December 23, 1999
    Date of Patent: October 14, 2003
    Assignee: PMC-Sierra Limited
    Inventor: Heng Liao
  • Publication number: 20020116682
    Abstract: A Viterbi decoder for decoding a convolutional code. For each possible state, an accumulated error AE is maintained at 66. As each codeword Rx-GP is received, the errors between it and the code groups of all the transitions are determined at 65. For each possible new state, logic 68 determines the errors of the two transitions leading from old states to that new state, adds them to the accumulated errors of those two old states, and determines the smaller of the two sums. Path logic 67 records the corresponding transition, updating a record of the path leading to the new state. Tracing back along a path a predetermined and sufficiently large number of transitions, the input bit or bits corresponding to the transition so reached are taken as the next bit or bits in the stream of decoded bits.
    Type: Application
    Filed: July 12, 2001
    Publication date: August 22, 2002
    Applicant: PMC Sierra Limited
    Inventor: Cormac Brick
  • Publication number: 20020112211
    Abstract: A Viterbi decoder for decoding a convolutional code. For each possible state, an accumulated error AE is maintained at 66. As each codeword Rx-GP is received, the errors between it and the code groups of all the transitions are determined at 65. For each possible new state, logic 68 determines the errors of the two transitions leading from old states to that new state, adds them the accumulated errors of those two old states, and determines the smaller of the two sums. Path logic 67 records the corresponding transition, updating a record of the path leading to the new state. Tracing back along a path a predetermined and sufficiently large number of transitions, the input bit or bits corresponding to the transition so reached are taken as the next bit or bits in the stream of decoded bits. The unit 57 comprises a tree of comparators fed with the accumulated errors. The accumulated errors are limited, before being fed to unit 57, by a set of limiters 76 to values less than the maximum error upper bound.
    Type: Application
    Filed: July 12, 2001
    Publication date: August 15, 2002
    Applicant: PMC Sierra Limited
    Inventor: Cormac Brick