Abstract: Alignment-enabled secondary nodes of a DAMA network monitor the alignment of for-transmission data as it is received, and actively align the data frames into encoded blocks such that the number of blocks occupied by encoded data resulting from an unencoded datastream of a particular length is predictable rather than variable. In some embodiments, the network is an Ethernet passive optical network and the alignment includes aligning a XGMII word having a start control code to a first position in a 72 bit word input to a 66B/66B encoder, thereby encoding a start-of-frame (/S/) code to a first byte of an encoded first Ethernet 66b block.

Abstract: A system and/or method for metering and marking packets of data incoming into a communication system having in some embodiments primary and secondary meter selectors, primary and secondary metering processors and a pipeline and wrapper interface controller. Further methods involve measuring an incoming microflow against one or two specified temporal profiles using a two-level metering hierarchy.

Abstract: Methods and apparatus for finding a match between a target bit pattern and multiple filter bit patterns. A filter array is created from the filter bit patterns and at least one intermediate array is generated from the filter array. Specific columns of the intermediate arrays are then extracted based on bit values of the target bit pattern. A row by row AND operation is performed on these columns to arrive at a match vector. the match vector identifies which of the filter bit patterns in the filter array match the target bit pattern. The method is implemented by using multiple classifier elements operating in parallel with each classifier element handling multiple filter bit patterns.

Abstract: Methods and devices for controlling and managing data flow and data transmission rates. A feedback mechanism is used in conjunction with measuring output transmission rates to control the input transmission rates, changing conditions can be accounted for an excess output transmission capacity can be shared among numerous input ports. Similarly, by using maximum and minimum rates which can be requested from an output port, minimum transmission rates can be guaranteed for high priority traffic while capping maximum output rates for low priority traffic. By combining the two ideas of feedback rate control and placing maximum requestable transmission rates, a more equitable output sharing mechanism arises. The measured output transmission rate is used to control and recalculate the maximum requestable output transmission rate for incoming flows, thereby allowing for changing network and data flow conditions.

Abstract: A phase detector customized for Clock Synthesis Unit (CSU) is disclosed. The phase detector improves jitter performance by providing minimal activity on VCO control lines and pushing ripple frequency to one octave higher, while maintaining wide linear characteristic. Moreover, it provides a frequency-scalable circuit that unlike a conventional phase-and-frequency detector (PFD), does not rely on asynchronous elements.

Abstract: Methods and devices for controlling and managing data flow and data transmission rates. A feedback mechanism is used in conjunction with measuring output transmission rates to control the input transmission rates, changing conditions can be accounted for an excess output transmission capacity can be shared among numerous input ports. Similarly, by using maximum and minimum rates which can be requested from an output port, minimum transmission rates can be guaranteed for high priority traffic while capping maximum output rates for low priority traffic. By combining the two ideas of feedback rate control and placing maximum requestable transmission rates, a more equitable output sharing mechanism arises. The measured output transmission rate is used to control and recalculate the maximum requestable output transmission rate for incoming flows, thereby allowing for changing network and data flow conditions.

Abstract: Methods and apparatus for reducing the search space processed by mask matching methods. The search space is reduced by grouping the candidate bit patterns into groups and subgroups that have internal bit agreement between the members. By only applying the mask matching methods to a select number of groups selected by their bit agreement with the target bit pattern, the computation time and memory requirement of the mask matching method is reduced.

Abstract: Methods, systems, and apparatus for processing packet fragments for reassembly into packets. Datastreams containing packet fragments are received and data corresponding to different channels are segregated. For each channel, data is then aggregated to recreate packet fragments. Once the fragments are recreated, they are, if required, resequenced using a two-tier memory mapping structure where only pointers, and not the fragments, are manipulated. After resequencing fragments to reassemble the packet, the reassembled packet is dispatched to its ultimate destination. The present invention also provides a method of load balancing between multiple links when packet fragments are transmitted from a fragmenting node through a multiple link bundle.

Abstract: Methods and devices for scheduling data transmission processing based on the size of the data transmission unit and a predetermined increment value. A scheduler has slots which represent specific amounts of time in which a queue of data transmission units to be processed is represented. An indicator determines which slot and thereby which queue is being examined. Each queue is assigned a specific increment value and each data transmission unit in a queue is assigned a count value based on the size of the data transmission unit. When a data transmission unit is at the head of the queue and is a candidate for processing, if the count value is greater than a predetermined value then the queue and thereby the data transmission unit at the head of the queue is rescheduled at a later time. This is effected by assigning the queue to a subsequent slot in the scheduler. The subsequent slot in the scheduler is determined based on the given increment value for that queue.

Abstract: Over-sampled timing signal jitter tolerance is improved in a q-times over-sampled architecture by phase-sampling the timing signal to produce a plurality of input phase samples &phgr;in, where &phgr;in&egr;{&phgr;1, &phgr;2, . . . , &phgr;q}. An output phase value &phgr;out=&phgr;in is initialized for each input sample &phgr;in. A difference vector di is derived for each input sample &phgr;in, where di=Fj(n,k). F denotes a vector operation, n is the number of input samples, k is a pre-defined threshold value, and j represents a filter order value. A predefined scaling coefficient ai is applied to each difference vector di to produce a corresponding set of scaled difference vectors ai di. The scaled difference vectors are summed: d j = ∑ i = 1 n ⁢ a i ⁢ d i .

Abstract: A data traffic management system that has the capability of writing data to the buffer memory at twice its normal rate. The data traffic management system uses a pointer structure that can reference either a single or a dual segment memory bank. A dual segment memory bank enhances the write capability of the data traffic management system by allowing two segments to be simultaneously written to both segment memory banks, with one segment being written to each bank. A pointer data structure with a single/dual indicator (S/D indicator) is used for referencing the memory banks. If the S/D indicator has a D entry, then a dual segment memory bank is addressed. The S/D indicator will have an S entry if a single segment memory bank is addressed. Based on the contents of the S/D indicator, either a single fixed size data segment is written to a single memory bank or two fixed size data segments are written to a dual segment memory bank.

Abstract: Methods and devices for arranging memory access operations to minimize memory bank conflicts between such operations. A fixed pattern of memory access operations is implemented to minimize the effects of a transition between a read memory access operation and a write memory access operation. A write-read-gap (WRG) set pattern of a write memory access operation followed by a read memory access operation and then followed by a set gap when no memory access operation may be undertaken, meets the particular requirements of RDRAM. Within the WRG pattern, read addresses and write addresses are selected to minimize memory bank access conflicts. Such selections are assisted in increasing the efficiency of the memory access operations by defining a set frame size of a specific number of repetitions of the WRG pattern. All memory access operations are then rearranged to conform to the WRG pattern and, the repetitions of the WRG pattern are divided into frames having a size equal to that of the defined frame size.

Abstract: A method and apparatus for switching n data streams for input and output of the data streams by an n input, n output data store without data loss. The data store is divided into n separate storage arrays and each data stream is divided into n equal-sized pieces. Then, during each one of n separate time units, one data stream piece is written into a corresponding one of the storage arrays; or, one data stream piece is read from a corresponding one of the storage arrays. For each data stream, during each time unit i, where 1≦i≦n an ith data stream piece is written into an ith one of the storage arrays, or an ith piece is read from an ith storage array. During each jth time unit, where 1≦j≦n, one data stream piece Pij is written into an ith storage array, or one piece Pij is read from an ith storage array.

Abstract: A method of communicating data frames between nodes in a network comprised of one or more end system nodes where each end system node has a unidirectional ingress port and a unidirectional egress port. The method comprises transmitting a data frame from an egress port of one end system node to the ingress port of another end system node, the receiving end system node then determining whether it is the final destination for the data frame. If the receiving end system node is the final destination of the data frame, the receiving end system node absorbs the message. If not, the receiving end system node buffers and then retransmits the data frame through its own egress port. The method provides scalability, low cost, distributed pipeline scheduling, maximum complexity of the network fabric, and maximum speed.

Abstract: An apparatus and method for restoring digital pulses within a data transmission system which have degraded due to the attenuation and distortion inherent in a data transmission medium. The apparatus comprises an adaptive equalizer which receives signals from the data transmission medium, while the method by which the digital pulses are restored comprises: storing plural equalizer transfer function control values in a memory, passing the signal through an equalizer having a controllable transfer function, comparing a characteristic of the output signal of the equalizer with a reference signal and producing a difference signal, using the difference signal to select a set of stored transfer function control values from the memory, controlling the equalizer from the selected transfer function control values so as to minimize their difference from the reference signal. This apparatus and method are suitable for high-speed applications such as T1 and E1, requiring minimal configuration by the user.

Abstract: A circuit for correcting baseline wander in a transmitter which includes a main signal current driver driving a first winding of a two-winding transformer which first winding is in parallel with a termination impedance matching load, in which a compensation current driver is coupled in parallel with the main signal current driver for adding its current to current of the main signal current driver. A correction signal control input is provided to the compensation driver. A sample-and-hold circuit is connected across the first winding, an error amplifier having a first pair of inputs is connected across the first winding and a second pair of inputs are connected to the output of the sample and hold circuit. These provide an error signal resulting from a difference of signals appearing at its respective pairs of inputs.

Abstract: A plurality of time-division multiplexed data streams which are merged into a single data stream containing a plurality of data words and which are characterized by state vectors, are concurrently processed. The state vectors are stored in a read-write memory having a plurality of addressable memory locations. During an initial clock cycle, a pipeline receives an input data word from one of the data streams, an input state vector characterizing that data stream, and the memory location address of the input state vector. During one or more intermediate clock cycles, the pipeline processes the input data word and the input state vector to yield an output data word and an output state vector. During a final clock cycle, the pipeline transfers the output data word to an outgoing data stream, and transfers the output state vector into the aforementioned memory location address. A controller coupled to the memory and to the pipeline synchronizes operation thereof.

Abstract: A method of phase detecting a data input NRZ signal comprises applying the input data signal to a pair of parallel channels each comprising the same phase delay, and each clocked using the same clock signal. The phase delayed input data signal is coupled to respective inputs of a pair of phase comparators. The input data signal is coupled to a further channel comprising the same phase delay, and the further channel is clocked using the same clock signal. The phase delayed input signal is passed from the further channel through a further delay which is a fraction of that same phase delay, and the further delay is clocked using the clock signal. The further delayed input data signal is applied to another input of one of the phase comparators. The input data signal is applied through another phase delay which has the fraction of the aforenoted same phase delay (but is unclocked), to another input of the other of the phase comparators. Output signals are obtained from each of the phase comparators.

Abstract: A method of providing broadband communication services to a subscriber comprised of providing first broadband services from a central office via an ATM link to a neighborhood pedestal system, providing time division multiplex (TDM) services including voice communication services from the central office via a TDM link to the neighborhood pedestal system, providing a SONET-ATM communication link from the neighborhood pedestal system over two unshielded pair of twisted wires to a user-to-network interface (UNI) at a subscriber location, and providing ATM services over the SONET-ATM communication link and providing integrated services digital network (ISDN) or voice services within a SONET-ATM data frame using timing of the SONET-ATM communication link, to the UNI, whereby ATM, ISDN and voice services are provided between the neighborhood pedestal system and the subscriber location over the unshielded wires.

Abstract: A phase detector for controlling a phase locked loop having a voltage controlled oscillator. A counter is clocked by a clock signal produced by the voltage controlled oscillator. A latch coupled to the counter is clocked by a modulated clock signal to latch values output by the counter. The modulated clock signal is produced by a phase modulator which modulates a synchronization clock reference signal. An accumulator coupled to the latch and clocked by the modulated clock signal receives and averages the latch values to produce a phase error signal representative of phase difference between the voltage controlled oscillator clock signal and the synchronization clock reference signal. The phase error signal is coupled to the voltage controlled oscillator to reduce the phase difference. The phase modulator modulates a rising edge of the synchronization clock reference signal with a modulation signal having modulation frequencies outside the loop bandwidth of the phase locked loop.