Patents Assigned to POET Technologies, Inc.
  • Patent number: 11906798
    Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 20, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
  • Patent number: 11867946
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400° C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: January 9, 2024
    Assignee: POET Technologies, Inc.
    Inventors: William Ring, Miroslaw Florjanczyk
  • Patent number: 11670908
    Abstract: The invention described herein pertains to the structure and formation of an optical device that includes a planar laser and a waveguide. The planar laser has a large lateral QW-containing layer and a tapered section in a transition portion of the device structure that enable low diode leakage currents and facilitate transition of the optical signal from the laser to a transition waveguide, and in some embodiments, to a dilute waveguide.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 6, 2023
    Assignee: POET Technologies, Inc.
    Inventor: Suresh Venkatesan
  • Patent number: 11448827
    Abstract: A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 20, 2022
    Assignee: POET Technologies, Inc.
    Inventor: Yee Loy Lam
  • Patent number: 11156779
    Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 26, 2021
    Assignee: POET Technologies, Inc.
    Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
  • Patent number: 11099338
    Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: August 24, 2021
    Assignee: POET Technologies, Inc.
    Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
  • Patent number: 10983277
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: January 18, 2020
    Date of Patent: April 20, 2021
    Assignee: POET Technologies, Inc.
    Inventors: William Ring, Miroslaw Florjanczyk
  • Patent number: 10976497
    Abstract: The invention described herein pertains to the structure and formation of dual core waveguide structures and to the formation of optical devices including spot size converters from these dual core waveguide structure for the receiving and routing of optical signals on substrates, interposers, and sub-mount assemblies.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 13, 2021
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Miroslaw Florjanczyk, Trevor Hall, Peng Liu, Jing Yang
  • Patent number: 10976496
    Abstract: The invention described herein pertains to the structure and formation of dual core waveguide structures and to the formation of optical devices including spot size converters from these dual core waveguide structure for the receiving and routing of optical signals on substrates, interposers, and sub-mount assemblies.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: April 13, 2021
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Miroslaw Florjanczyk, Trevor Hall, Peng Liu, Jing Yang
  • Patent number: 10962715
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 30, 2021
    Assignee: POET Technologies, Inc.
    Inventors: William Ring, Suresh Venkatesan
  • Patent number: 10811841
    Abstract: A split electrode vertical cavity optical device includes an n-type ohmic contact layer, first through fifth ion implant regions, cathode and anode electrodes, first and second injector terminals, and p and n type modulation doped quantum well structures. The cathode electrode and the first and second ion implant regions are formed on the n-type ohmic contact layer. The third ion implant region is formed on the first ion implant region and contacts the p-type modulation doped QW structure. The fourth ion implant region encompasses the n-type modulation doped QW structure. The first and second injector terminals are formed on the third and fourth ion implant regions, respectively. The fifth ion implant region is formed above the n-type modulation doped QW structure and the anode electrode is formed above the fifth ion implant region.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 20, 2020
    Assignee: POET Technologies, Inc.
    Inventor: Geoff W. Taylor
  • Patent number: 10795079
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 6, 2020
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Loy Yee Lam
  • Patent number: 10718905
    Abstract: A method for depositing silicon oxynitride film structures is provided that is used to form planar waveguides. These film structures are deposited on substrates and the combination of the substrate and the planar waveguide is used in the formation of optical interposers and subassemblies. The silicon oxynitride film structures are deposited using low thermal budget processes and hydrogen-free oxygen and hydrogen-free nitrogen precursors to produce planar waveguides that exhibit low losses for optical signals transmitted through the waveguide of 1 dB/cm or less. The silicon oxynitride film structures and substrate exhibit low stress levels of less than 20 MPa.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 21, 2020
    Assignee: POET Technologies, Inc.
    Inventors: William Ring, Miroslaw Florjanczyk, Suresh Venkatesan
  • Patent number: 10663660
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: May 26, 2020
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Loy Yee Lam
  • Patent number: 10656338
    Abstract: A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 19, 2020
    Assignee: POET Technologies, Inc.
    Inventor: Yee Loy Lam
  • Patent number: 10601198
    Abstract: A Dual-wavelength hybrid (DWH) device includes an n-type ohmic contact layer, cathode and anode terminal electrodes, first and second injector terminal electrodes, p-type and n-type modulation doped QW structures, and first through sixth ion implant regions. The first injector terminal electrode is formed on the third ion implant region that contacts the p-type modulation doped QW structure and the second injector terminal electrode is formed on the fourth ion implant region that contacts the n-type modulation doped QW structure. The DWH device operates in at least one of a vertical cavity mode and a whispering gallery mode. In the vertical cavity mode, the DWH device converts an in-plane optical mode signal to a vertical optical mode signal, whereas in the whispering gallery mode the DWH device converts a vertical optical mode signal to an in-plane optical mode signal.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 24, 2020
    Assignee: POET Technologies, Inc.
    Inventor: Geoff W. Taylor
  • Patent number: 10551561
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 4, 2020
    Assignee: POET Technologies, Inc.
    Inventors: William Ring, Miroslaw Florjanczyk
  • Patent number: 10530125
    Abstract: A vertical cavity surface emitting laser (VCSEL) is formed on a substrate. The VCSEL includes a layer structure and one or more distributed Bragg reflector (DBR) mirrors formed on at least one of the layer structure or the substrate. The layer structure generates an optical signal at a first wavelength based on a control current received from a transistor that is formed on the substrate. Rare earth ions (REIs) are deposited in the one or more DBR mirrors such that the one or more DBR mirrors receive the optical signal at the first wavelength and generate the optical signal at a second wavelength.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 7, 2020
    Assignee: POET Technologies, Inc.
    Inventor: Suresh Venkatesan