Abstract: A method for forming a lateral DMOS transistor comprises: a) forming a first doped region of a first conductivity type in a semiconductor substrate of the first conductivity type; b) forming an epitaxial layer on the substrate; c) forming a second doped region of the first conductivity type in the epitaxial layer; and d) forming a body region of the first conductivity type in the epitaxial layer. The process of forming the first and second doped regions and the body region includes thermally diffusing dopants in these regions so that the first and second doped regions diffuse and meet one another. The body region also meets and contacts the second doped region. The body region is electrically coupled to the substrate via the first and second doped regions. Source and drain regions are then formed in the epitaxial layer. By forming the transistor in this manner, the electrical resistance between the body region and substrate can be reduced or minimized.

Abstract: An improved FET is described in which a conductive layer connects the source structure to a truncated source extension which underlies an insulative gate layer and connects to a channel region. The conductive layer is of substantially lower resistivity than the source extension, thereby significantly reducing the lateral resistance of the device to diminish losses and reduce the likelihood of a parasitic bipolar transistor turning on. The invention can be implemented in both vertical and lateral devices. For a lateral device the drain is connected by a low resistance conductive layer to the gate region in a manner similar to the source.