Patents Assigned to Polystak, Inc.
  • Patent number: 8466008
    Abstract: A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: June 18, 2013
    Assignee: Polystak, Inc.
    Inventor: Tae Seung Chung
  • Patent number: 8310041
    Abstract: A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: November 13, 2012
    Assignee: Polystak, Inc.
    Inventor: Tae Seung Chung
  • Publication number: 20120038062
    Abstract: A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips.
    Type: Application
    Filed: November 24, 2010
    Publication date: February 16, 2012
    Applicant: Polystak, Inc.
    Inventor: Tae Seung CHUNG