Abstract: This invention describes a compilation method of extracting and implementing an accelerator control program from an application source code in a processor based system. The application source code comprises arrays and loops. The input application source code is sequential, with loop, branch and call control structures, while the generated output of this invention has parallel execution semantics. The compilation method comprises the step of performing loop nest analysis, transformations and backend processes. The step of loop nest analysis consists of dependence analysis and pointer analysis. Dependence analysis determines the conflicts between the various references to arrays in the loop, and pointer analysis determines if two pointer references in a loop are in conflict. Transformations convert the loops from their original sequential execution semantics to parallel execution semantics. The back-end process determines the parameters and memory map of the accelerator and the hardware dependent software.

Abstract: A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packing criteria and analysing the data pattern and determining the impact of offset direction on data packing. If the packing criteria are met, the data is compacted and fetched in four bytes or two half-words in one transaction by performing a full-word transfer instead of a partial transfer. If the packing criteria are not met, a single byte or a single half word is fetched. This invention provides a system for reducing data transfer overheads. The system comprises of an external address generation unit for generating external memory addresses and corresponding byte enables and a read local address generation unit for generating internal memory addresses and corresponding byte enables.

Abstract: A system and method of designing an accelerator for a processor-based system. The accelerator design problem is partitioned into a data communicate module design problem and a data compute core module design problem. The hardware design of the data communicate module is achieved through a predetermined communication template which is customized for the particular application. The communication template has individual configurable communication components and a programmable control flow path. The components of the communicate template include a host bus interface, a memory bus interface, a direct memory access, a local memory and a control module. The combination of the communication components in a single configurable communication template and their optimized interconnections increase the speed of data transfer and data control processes in the accelerator.